SC16C2552IA44,529 NXP Semiconductors, SC16C2552IA44,529 Datasheet - Page 18

IC UART DUAL W/FIFO 44-PLCC

SC16C2552IA44,529

Manufacturer Part Number
SC16C2552IA44,529
Description
IC UART DUAL W/FIFO 44-PLCC
Manufacturer
NXP Semiconductors
Datasheet

Specifications of SC16C2552IA44,529

Features
2 Channels
Number Of Channels
2, DUART
Fifo's
16 Byte
Voltage - Supply
2.5V, 3.3V, 5V
With False Start Bit Detection
Yes
With Modem Control
Yes
With Cmos
Yes
Mounting Type
Surface Mount
Package / Case
44-LCC (J-Lead)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
568-1186-5
935270026529
SC16C2552IA44-S

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
SC16C2552IA44,529
Manufacturer:
NXP Semiconductors
Quantity:
10 000
Philips Semiconductors
9397 750 11636
Product data
7.5 Line Control Register (LCR)
The Line Control Register is used to specify the asynchronous data communication
format. The word length, the number of stop bits, and the parity are selected by
writing the appropriate bits in this register.
Table 12:
Table 13:
Table 14:
Table 15:
Bit
7
6
5-3
2
1-0
LCR[5]
X
X
0
0
1
LCR[2]
0
1
1
LCR[1]
0
0
1
1
Line Control Register bits description
LCR[5] parity selection
LCR[2] stop bit length
LCR[1-0] word length
LCR[4]
X
0
1
0
1
Word length
5, 6, 7, 8
5
6, 7, 8
LCR[0]
0
1
0
1
Symbol
LCR[7]
LCR[6]
LCR[5-3]
LCR[2]
LCR[1-0]
Rev. 03 — 20 June 2003
LCR[3]
0
1
1
1
1
Word length
5
6
7
8
Description
Divisor latch enable. The internal baud rate counter latch and
Enhance Feature mode enable.
Set break. When enabled, the Break control bit causes a break
condition to be transmitted (the TX output is forced to a logic 0
state). This condition exists until disabled by setting LCR[6] to a
logic 0.
Programs the parity conditions (see
Stop bits. The length of stop bit is specified by this bit in
conjunction with the programmed word length (see
Word length bits 1, 0. These two bits specify the word length to be
transmitted or received (see
Logic 0 = Divisor latch disabled (normal default condition).
Logic 1 = Divisor latch enabled.
Logic 0 = no TX break condition (normal default condition)
Logic 1 = forces the transmitter output (TX) to a logic 0 for
alerting the remote receiver to a line break condition.
Logic 0 or cleared = default condition.
Logic 0 or cleared = default condition.
Stop bit length (bit times)
1
1-
2
Dual UART with 16-byte transmit and receive FIFOs
1
2
Parity selection
no parity
ODD parity
EVEN parity
force parity ‘1’
forced parity ‘0’
Table
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
15).
Table
SC16C2552
13).
Table
14).
18 of 38

Related parts for SC16C2552IA44,529