SC16C550IA44,529 NXP Semiconductors, SC16C550IA44,529 Datasheet - Page 14

• Manufacturer Part Number: SC16C550IA44,529
• Description: IC UART SINGLE W/FIFO 44-PLCC
• Manufacturer: NXP Semiconductors

Specifications of SC16C550IA44,529

• Features: Programmable
• Number Of Channels: 1, UART
• Fifo's: 16 Byte
• Voltage - Supply: 2.5V, 3.3V, 5V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Package / Case: 44-LCC (J-Lead)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-3264-5; 935270058529; SC16C550IA44-S

Philips Semiconductors
9397 750 11619
Product data
6.5 Special feature software flow control
6.6 Hardware/software and time-out interrupts
A special feature is provided to detect an 8-bit character when EFR[5] is set. When
8-bit character is detected, it will be placed on the user-accessible data stack along
with normal incoming RX data. This condition is selected in conjunction with
EFR[0-3]. Note that software flow control should be turned off when using this special
mode by setting EFR[0-3] to a logic 0.
The SC16C550 compares each incoming receive character with Xoff2 data. If a
match exists, the received data will be transferred to the FIFO, and ISR[4] will be set
to indicate detection of a special character. Although
registers”
number of bits is dependent on the programmed word length. Line Control Register
bits LCR[0-1] define the number of character bits, i.e., either 5 bits, 6 bits, 7 bits or
8 bits. The word length selected by LCR[0-1] also determine the number of bits that
will be used for the special character comparison. Bit 0 in the X-registers corresponds
with the LSB bit for the receive character.
Three special interrupts have been added to monitor the hardware and software flow
control. The interrupts are enabled by IER[5-7]. Care must be taken when handling
these interrupts. Following a reset, the transmitter interrupt is enabled, the SC16C550
will issue an interrupt to indicate that the Transmit Holding Register is empty. This
interrupt must be serviced prior to continuing operations. The LSR register provides
the current singular highest priority interrupt only. It could be noted that CTS and RTS
interrupts have lowest interrupt priority. A condition can exist where a higher priority
interrupt may mask the lower priority CTS/RTS interrupt(s). Only after servicing the
higher pending interrupt will the lower priority CTS/TRS interrupt(s) be reflected in the
status register. Servicing the interrupt without investigating further interrupt conditions
can result in data errors.
When two interrupt conditions have the same priority, it is important to service these
interrupts correctly. Receive Data Ready and Receive Time Out have the same
interrupt priority (when enabled by IER[3]). The receiver issues an interrupt after the
number of characters have reached the programmed trigger level. In this case, the
SC16C550 FIFO may hold more characters than the programmed trigger level.
Following the removal of a data byte, the user should re-check LSR[0] for additional
characters. A Receive Time Out will not occur if the receive FIFO is empty. The
time-out counter is reset at the center of each stop bit received or each time the
receive holding register (RHR) is read. The actual time-out value is 4 character time,
including data information length, start bit, parity bit, and the size of stop bit, i.e., 1 ,
1.5 , or 2 bit times.
shows each X-Register with eight bits of character information, the actual
Rev. 05 — 19 June 2003
UART with 16-byte FIFO and IrDA encoder/decoder
Table 8 “SC16C550 internal
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
SC16C550
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