SC16C654IB64,151 NXP Semiconductors, SC16C654IB64,151 Datasheet - Page 27
![IC UART QUAD W/FIFO 64-LQFP](/photos/6/98/69856/568-64-lqfp_sot314-2_sml.jpg)
SC16C654IB64,151
Manufacturer Part Number
SC16C654IB64,151
Description
IC UART QUAD W/FIFO 64-LQFP
Manufacturer
NXP Semiconductors
Datasheet
1.SC16C654DIB64151.pdf
(52 pages)
Specifications of SC16C654IB64,151
Number Of Channels
4, QUART
Fifo's
64 Byte
Voltage - Supply
2.5V, 3.3V, 5V
With Auto Flow Control
Yes
With Irda Encoder/decoder
Yes
With False Start Bit Detection
Yes
With Modem Control
Yes
With Cmos
Yes
Mounting Type
Surface Mount
Package / Case
64-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
568-3283
935270052151
SC16C654IB64-S
935270052151
SC16C654IB64-S
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
SC16C654IB64,151
Manufacturer:
NXP Semiconductors
Quantity:
10 000
Philips Semiconductors
9397 750 11617
Product data
7.6 Modem Control Register (MCR)
Table 16:
Table 17:
Table 18:
This register controls the interface with the modem or a peripheral device.
Table 19:
LCR[5]
X
0
0
1
1
LCR[2]
0
1
1
LCR[1]
0
0
1
1
Bit
7
6
Symbol
MCR[7]
MCR[6]
LCR[5] parity selection
LCR[2] stop bit length
LCR[1-0] word length
Modem Control Register bits description
LCR[4]
X
0
1
0
1
Word length
5, 6, 7, 8
5
6, 7, 8
LCR[0]
0
1
0
1
Quad UART with 64-byte FIFO and infrared (IrDA) encoder/decoder
Rev. 04 — 19 June 2003
Description
Clock select.
IR enable.
LCR[3]
0
1
1
1
1
Word length
5
6
7
8
Logic 0 = Divide-by-1. The input clock (crystal or external) is
divided by 16 and then presented to the Programmable Baud Rate
Generator (BGR) without further modification, i.e., divide-by-1.
(normal default condition).
Logic 1 = Divide-by-4. The divide-by-1 clock described in MCR[7] =
a logic 0, if further divided by four. Also see
“Programmable baud rate
Logic 0 = Enable the standard modem receive and transmit
input/output interface (normal default condition).
Logic 1 = Enable infrared IrDA receive and transmit inputs/outputs.
While in this mode, the TX/RX output/inputs are routed to the
infrared encoder/decoder. The data input and output levels will
conform to the IrDA infrared interface requirement. As such, while
in this mode, the infrared TX output will be a logic 0 during idle data
conditions.
Stop bit length (bit times)
1
1-
2
1
2
Parity selection
no parity
ODD parity
EVEN parity
force parity ‘1’
forced parity ‘0’
generator”.
SC16C654/654D
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Section 6.11
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