SC16C750IB64,151 NXP Semiconductors, SC16C750IB64,151 Datasheet - Page 17

• Manufacturer Part Number: SC16C750IB64,151
• Description: IC UART SINGLE W/FIFO 64-LQFP
• Manufacturer: NXP Semiconductors

Specifications of SC16C750IB64,151

• Number Of Channels: 1, UART
• Fifo's: 64 Byte
• Voltage - Supply: 2.5V, 3.3V, 5V
• With Auto Flow Control: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-3287; 935270054151; SC16C750IB64-S

Philips Semiconductors
9397 750 11623
Product data
7.1 Transmit (THR) and Receive (RHR) Holding Registers
7.2 Interrupt Enable Register (IER)
The serial transmitter section consists of an 8-bit Transmit Hold Register (THR) and
Transmit Shift Register (TSR). The status of the THR is provided in the Line Status
Register (LSR). Writing to the THR transfers the contents of the data bus (D7-D0) to
the THR, providing that the THR or TSR is empty. The THR empty flag in the LSR
register will be set to a logic 1 when the transmitter is empty or when data is
transferred to the TSR. Note that a write operation can be performed when the THR
empty flag is set (logic 0 = FIFO full; logic 1 = at least one FIFO location available).
The serial receive section also contains an 8-bit Receive Holding Register (RHR).
Receive data is removed from the SC16C750 and receive FIFO by reading the RHR
register. The receive section provides a mechanism to prevent false starts. On the
falling edge of a start or false start bit, an internal receiver counter starts counting
clocks at the 16 clock rate. After 7-
the center of the start bit. At this time the start bit is sampled, and if it is still a logic 0
it is validated. Evaluating the start bit in this manner prevents the receiver from
assembling a false character. Receiver status codes will be posted in the LSR.
The Interrupt Enable Register (IER) masks the interrupts from receiver ready,
transmitter empty, line status and modem status registers. These interrupts would
normally be seen on the INT output pin.
Table 9:
Bit
7-6
5
4
3
2
Symbol
IER[7],
IER[6]
IER[5]
IER[4]
IER[3]
IER[2]
Interrupt Enable Register bits description
Description
Not used.
Low power mode.
Sleep mode.
Modem Status Interrupt.
Receive Line Status interrupt. This interrupt will be issued whenever a fully
assembled receive character is transferred from RSR to the RHR/FIFO,
i.e., data ready, LSR[0].
Rev. 04 — 20 June 2003
Logic 0 = Disable low power mode (normal default condition).
Logic 1 = Enable low power mode.
Logic 0 = Disable sleep mode (normal default condition).
Logic 1 = Enable sleep mode. See
Logic 0 = Disable the modem status register interrupt (normal default
condition).
Logic 1 = Enable the modem status register interrupt.
Logic 0 = Disable the receiver line status interrupt (normal default
condition).
Logic 1 = Enable the receiver line status interrupt.
1
2
clocks, the start bit time should be shifted to
Section 6.7 “Sleep mode”
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
UART with 64-byte FIFO
SC16C750
for details.
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