SC16C754IA68,529 NXP Semiconductors, SC16C754IA68,529 Datasheet - Page 20
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SC16C754IA68,529
Manufacturer Part Number
SC16C754IA68,529
Description
IC UART QUAD W/FIFO 68-PLCC
Manufacturer
NXP Semiconductors
Datasheet
1.SC16C754IA68529.pdf
(49 pages)
Specifications of SC16C754IA68,529
Number Of Channels
4, QUART
Fifo's
64 Byte
Voltage - Supply
2.5V, 3.3V, 5V
With Auto Flow Control
Yes
With False Start Bit Detection
Yes
With Modem Control
Yes
Mounting Type
Surface Mount
Package / Case
68-LCC (J-Lead)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
568-3291-5
935270056529
SC16C754IA68-S
935270056529
SC16C754IA68-S
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
SC16C754IA68,529
Manufacturer:
NXP Semiconductors
Quantity:
10 000
Philips Semiconductors
7. Register descriptions
9397 750 11618
Product data
Each register is selected using address lines A0, A1, A2, and in some cases, bits
from other registers. The programming combinations for register selection are shown
in
Table 9:
[1]
[2]
[3]
[4]
[5]
[6]
A2
0
0
0
0
1
1
1
1
0
0
0
1
1
1
1
1
1
1
Fig 13. Crystal oscillator connection.
Table
MCR[7] can only be modified when EFR[4] is set.
Accessed by a combination of address pins and register bits.
Accessible only when LCR[7] is logic 1.
Accessible only when LCR is set to 10111111 (xBF).
Accessible only when EFR[4] = 1 and MCR[6] = 1, i.e., EFR[4] and MCR[6] are read/write enables.
Accessible only when CSA - CSD = 0, MCR[2] = 1, and loop-back is disabled (MCR[4] = 0).
A1
0
0
1
1
0
0
1
1
0
0
1
0
0
1
1
1
1
1
9.
Register map - read/write properties
A0
0
1
0
1
0
1
0
1
0
1
0
0
1
0
1
0
1
1
Read mode
receive holding register (RHR)
interrupt enable register (IER)
interrupt identification register (IIR)
line control register (LCR)
modem control register (MCR)
line status register (LSR)
modem status register (MSR)
scratchpad register (SPR)
divisor latch LSB (DLL)
divisor latch MSB (DLH)
enhanced feature register (EFR)
Xon1 word
Xon2 word
Xoff1 word
Xoff2 word
transmission control register (TCR)
trigger level register (TLR)
FIFO ready register
Rev. 04 — 19 June 2003
C1
47 pF
1.8432 MHz
X1
[2],
[2],
[2],
[2],
[4]
[4]
[4]
[4]
C2
100 pF
[2],
[6]
[2],
[2],
[3]
[2],
[3]
[5]
[1]
[2],
[2],
[4]
[5]
1.8432 MHz
C1
22 pF
Quad UART with 64-byte FIFO
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Write mode
transmit holding register (THR)
interrupt enable register
FIFO control register (FCR)
line control register
modem control register
scratchpad register
divisor latch LSB
divisor latch MSB
enhanced feature register
Xon1 word
Xon2 word
Xoff1 word
Xoff2 word
transmission control register
trigger level register
X1
1.5 k
C2
47 pF
SC16C754
002aaa169
[2],
[2],
[2],
[2],
[4]
[4]
[4]
[4]
[2],
[2],
[3]
[2],
[3]
[5]
[1]
[2],
20 of 49
[2],
[4]
[5]