SC16C2552IA44,518 NXP Semiconductors, SC16C2552IA44,518 Datasheet - Page 19

• Manufacturer Part Number: SC16C2552IA44,518
• Description: IC UART DUAL SOT187-2
• Manufacturer: NXP Semiconductors

Specifications of SC16C2552IA44,518

• Features: 2 Channels
• Number Of Channels: 2, DUART
• Fifo's: 16 Byte
• Voltage - Supply: 2.5V, 3.3V, 5V
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Package / Case: 44-LCC (J-Lead)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935270026518; SC16C2552IA44-T; SC16C2552IA44-T

Philips Semiconductors
9397 750 11636
Product data
7.6 Modem Control Register (MCR)
This register controls the interface with the modem or a peripheral device.
Table 16:
Bit
7-5
4
3
2
1
0
Symbol
MCR[7-5]
MCR[4]
MCR[3]
MCR[2]
MCR[1]
MCR[0]
Modem Control Register bits description
Rev. 03 — 20 June 2003
Description
Not used; initialized to a logic 0.
Loop-back. Enable the local loop-back mode (diagnostics). In this
mode the transmitter output TX and the receiver input RX, CTS, DSR,
CD, and RI are disconnected from the SC16C2552 I/O pins.
Internally the modem data and control pins are connected into a
loop-back data configuration (see
and transmitter interrupts remain fully operational. The Modem
Control Interrupts are also operational, but the interrupts’ sources are
switched to the lower four bits of the Modem Control. Interrupts
continue to be controlled by the IER register.
OP2, INTA/INTB enable. Used to control the modem CD signal in the
loop-back mode.
OP1. This bit is used in the Loop-back mode only. In the loop-back
mode, this bit is used to write the state of the modem RI interface
signal.
RTS
DTR
Logic 0 = Disable loop-back mode (normal default condition).
Logic 1 = Enable local loop-back mode (diagnostics).
Logic 0 = Forces INT (A-B) outputs to the 3-State mode and sets
OP2 to a logic 1 (normal default condition). In the loop-back mode,
sets CD internally to a logic 1.
Logic 1 = Forces the INT (A-B outputs to the active mode and sets
OP2 to a logic 0. In the loop-back mode, sets CD internally to a
logic 0.
Logic 0 = Force RTS output to a logic 1 (normal default condition).
Logic 1 = Force RTS output to a logic 0.
Logic 0 = Force DTR output to a logic 1 (normal default condition).
Logic 1 = Force DTR output to a logic 0.
Dual UART with 16-byte transmit and receive FIFOs
Figure
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
4). In this mode, the receiver
SC16C2552
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