SC16C550IA44,518 NXP Semiconductors, SC16C550IA44,518 Datasheet - Page 11

• Manufacturer Part Number: SC16C550IA44,518
• Description: IC UART SOT187-2
• Manufacturer: NXP Semiconductors

Specifications of SC16C550IA44,518

• Features: Programmable
• Number Of Channels: 1, UART
• Fifo's: 16 Byte
• Voltage - Supply: 2.5V, 3.3V, 5V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Package / Case: 44-LCC (J-Lead)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935270058518; SC16C550IA44-T; SC16C550IA44-T

Philips Semiconductors
9397 750 11619
Product data
Fig 5. Autoflow control (auto-RTS and auto-CTS) example.
D7 – D0
6.3.1 Auto-RTS (see
6.3 Autoflow control (see
FIFO
FIFO
RCV
XMT
Table 4:
Autoflow control is comprised of auto-CTS and auto-RTS. With auto-CTS, the CTS
input must be active before the transmitter FIFO can emit data. With auto-RTS, RTS
becomes active when the receiver needs more data and notifies the sending serial
device. When RTS is connected to CTS, data transmission does not occur unless the
receiver FIFO has space for the data; thus, overrun errors are eliminated using
UART 1 and UART 2 from a SC16C550 with the autoflow control enabled. If not,
overrun errors occur when the transmit data rate exceeds the receiver FIFO read
latency.
Auto-RTS data flow control originates in the receiver timing and control block (see
Figure 1 “Block
level. When the receiver FIFO level reaches a trigger level of 1, 4, or 8 (see
RTS is de-asserted. With trigger levels of 1, 4, and 8, the sending UART may send an
additional byte after the trigger level is reached (assuming the sending UART has
another byte to send) because it may not recognize the de-assertion of RTS until
after it has begun sending the additional byte. RTS is automatically reasserted once
the RX FIFO is emptied by reading the receiver buffer register. When the trigger level
is 14 (see
present on the RX line. RTS is reasserted when the RX FIFO has at least one
available byte space.
Selected trigger level
(characters)
1
4
8
14
ACE1
SERIAL TO
TO SERIAL
PARALLEL
PARALLEL
CONTROL
CONTROL
Figure
Flow control mechanism
FLOW
FLOW
diagram.”) and is linked to the programmed receiver FIFO trigger
Figure
8), RTS is de-asserted after the first data bit of the 16th character is
Rev. 05 — 19 June 2003
CTS
RTS
RX
TX
5)
INT pin activation
1
4
8
14
Figure
UART with 16-byte FIFO and IrDA encoder/decoder
TX
CTS
RX
RTS
5)
TO SERIAL
SERIAL TO
PARALLEL
PARALLEL
CONTROL
CONTROL
FLOW
FLOW
ACE2
Negate RTS or
send Xoff
4
8
12
14
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
FIFO
FIFO
XMT
RCV
SC16C550
002aaa048
Assert RTS or
send Xon
1
4
8
10
D7 – D0
Figure
11 of 52
7),