LM49370RL/NOPB National Semiconductor, LM49370RL/NOPB Datasheet - Page 14

• Manufacturer Part Number: LM49370RL/NOPB
• Description: IC AUDIO SUBSYSTEM 1.2W 49USMDXT
• Manufacturer: National Semiconductor
• Series: Boomer®, PowerWise®r
• Type: Class Dr

Specifications of LM49370RL/NOPB

• Output Type: 1-Channel (Mono) with Mono and Stereo Headphones
• Max Output Power X Channels @ Load: 1.2W x 1 @ 8 Ohm; 52mW x 2 @ 16 Ohm
• Voltage - Supply: 2.5 V ~ 5.5 V
• Features: 3D, Depop, I²C, I²S, Microphone, Mute, PCM, Shutdown, SPI, Standby, Volume Control
• Mounting Type: Surface Mount
• Package / Case: 49-MicroSMDxt
• Dc: 07+
• For Use With: LM49370RLEVAL - BOARD EVALUATION LM49370RL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: LM49370RLTR

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11.0 System Control
Method 1. I
11.1 I
In I
signals need a pull-up resistor according to I
11.2 I
The data on SDA line must be stable during the HIGH period of the clock signal (SCL). In other words, state of the data line can
only be changed when SCL is LOW.
11.3 I
START and STOP bits classify the beginning and the end of the I
from HIGH to LOW while SCL line is HIGH. STOP condition is defined as the SDA transitioning from LOW to HIGH while SCL is
HIGH. The I
free after STOP condition. During data transmission, I
repeated START conditions are equivalent, function-wise.
11.4 TRANSFERRING DATA
Every byte put on the SDA line must be eight bits long, with the most significant bit (MSB) being transferred first. Each byte of data
has to be followed by an acknowledge bit. The acknowledge related clock pulse is generated by the master. The transmitter releases
the SDA line (HIGH) during the acknowledge clock pulse. The receiver must pull down the SDA line during the 9
signifying an acknowledge. A receiver which has been addressed must generate an acknowledge after each byte has been re-
ceived.
After the START condition, the I
a data direction bit (R/W). The LM49370 address is 0011010
READ. The second byte selects the register to which the data will be written. The third byte contains data to write to the selected
register.
2
C mode the LM49370 pin SCL is used for the I
2
2
2
C SIGNALS
C DATA VALIDITY
C START AND STOP CONDITIONS
2
2
C Compatible Interface
C master always generates START and STOP bits. The I
2
C master sends a chip address. This address is seven bits long followed by an eight bit which is
2
C specification. The I
2
I
C clock SCL and the pin SDA is used for the I
2
C Signals: Data Validity
2
C master can generate repeated START conditions. First START and
2
. For the eighth bit, a “0” indicates a WRITE and a “1” indicates a
2
14
C session. START condition is defined as SDA signal transitioning
2
C slave address for LM49370 is 0011010
2
C bus is considered to be busy after START condition and
201917q1
201917q2
2
C data signal SDA. Both these
2
.
th
clock pulse,