LM49370RL/NOPB National Semiconductor, LM49370RL/NOPB Datasheet - Page 27

• Manufacturer Part Number: LM49370RL/NOPB
• Description: IC AUDIO SUBSYSTEM 1.2W 49USMDXT
• Manufacturer: National Semiconductor
• Series: Boomer®, PowerWise®r
• Type: Class Dr

Specifications of LM49370RL/NOPB

• Output Type: 1-Channel (Mono) with Mono and Stereo Headphones
• Max Output Power X Channels @ Load: 1.2W x 1 @ 8 Ohm; 52mW x 2 @ 16 Ohm
• Voltage - Supply: 2.5 V ~ 5.5 V
• Features: 3D, Depop, I²C, I²S, Microphone, Mute, PCM, Shutdown, SPI, Standby, Volume Control
• Mounting Type: Surface Mount
• Package / Case: 49-MicroSMDxt
• Dc: 07+
• For Use With: LM49370RLEVAL - BOARD EVALUATION LM49370RL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: LM49370RLTR

12.9 FURTHER NOTES ON PLL PROGRAMMING
The sigma-delta PLL Is designed to drive audio circuits requiring accurate clock frequencies of up to 30MHz with frequency errors
noise-shaped away from the audio band. The 5 bits of modulus control provide exact synchronization of 48kHz and 44.1kHz sample
rates from any common system clock. In systems where an isochronous I
synchronous to the sample rate should be used as input to the PLL (typically the I
then the PLL can be used to obtain a clock that is accurate to within 1Hz of the correct sample rate although this is highly unlikely
to be a problem.
F
11.2896
in
12.288
19.44
19.68
19.44
19.68
14.4
16.2
16.8
19.2
19.8
14.4
16.2
16.8
19.2
19.8
(MHz)
11
13
11
12
13
F
TABLE 10. Example PLL Settings for 48 kHz and 44.1 kHz Sample Rates in DAC MODE 00
s
44.1
44.1
44.1
44.1
44.1
44.1
44.1
44.1
44.1
44.1
44.1
(kHz)
48
48
48
48
48
48
48
48
48
48
20.5
16.5
13.5
20.5
11
13
27
14
13
27
11
13
12
17
16
11
M
4
9
8
5
9
19.53125
22.96875
55.78125
38.28125
39.0625
45.9375
45.9375
45.9375
40.625
55.125
55.125
30.625
30.625
37.5
62.5
100
100
60
60
50
50
N
FIGURE 7. PLL Overview
P
5
5
5
5
5
5
5
6
5
5
5
5
5
5
5
5
5
5
5
4
5
PLL_M
21
25
17
53
27
25
53
40
32
21
15
25
23
17
33
31
26
40
21
7
9
27
PLL_N
100
100
60
19
60
37
50
40
62
50
55
39
22
55
45
30
45
38
45
30
9
2
S data stream is the source of data to the DAC a clock
2
S clock). If no isochronous source is available,
PLL_N_MOD
17
16
20
16
31
30
20
25
30
30
20
0
0
0
0
0
0
4
2
4
9
PLL_P
11
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
7
9
201917r0
www.national.com
F
out
11.025
11.025
11.025
11.025
11.025
11.025
11.025
11.025
11.025
11.025
11.025
12
12
12
12
12
12
12
12
12
12
(MHz)