ADRF6602ACPZ-R7 Analog Devices Inc, ADRF6602ACPZ-R7 Datasheet
ADRF6602ACPZ-R7
Specifications of ADRF6602ACPZ-R7
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ADRF6602ACPZ-R7 Summary of contents
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FEATURES Rx mixer with integrated fractional-N PLL RF input frequency range: 1000 MHz to 3100 MHz Internal LO frequency range: 1550 MHz to 2150 MHz Input P1dB: 14.8 dBm Input IP3: 30 dBm IIP3 optimization via external pin SSB noise ...
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ADRF6602 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 RF Specifications .......................................................................... 3 Synthesizer/PLL Specifications ................................................... 4 Logic Input and Power Specifications ....................................... ...
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SPECIFICATIONS RF SPECIFICATIONS ambient temperature ( 25° using CDAC (0x0) and IP3SET (3.3 V), unless otherwise noted. Table 2. Parameter Test Conditions/Comments INTERNAL LO FREQUENCY RANGE RF INPUT FREQUENCY RANGE ±3 ...
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ADRF6602 SYNTHESIZER/PLL SPECIFICATIONS ambient temperature ( 25° 140 MHz; IIP3 optimized using CDAC (0x0) and IP3SET (3.3 V), unless otherwise noted. IF Table 3. Parameter Test Conditions/Comments SYNTHESIZER SPECIFICATIONS ...
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TIMING CHARACTERISTICS VCC2 = 5 V ± 5%. Table 5. Parameter Limit Unit min min min min min ...
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ADRF6602 ABSOLUTE MAXIMUM RATINGS Table 6. Parameter Supply Voltage, VCC1, VCC2, VCC_LO, VCC_MIX, VCC_V2I Digital I/O, CLK, DATA, LE IFP, IFN RF IN LOP, LON θ (Exposed Paddle Soldered Down) JA Maximum Junction Temperature Operating Temperature Range Storage Temperature Range ...
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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Table 7. Pin Function Descriptions Pin No. Mnemonic Description 1 VCC1 Power Supply for the 3.3 V LDO. Power supply voltage range is 4. 5.25 V. Each power supply pin should be decoupled ...
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ADRF6602 Pin No. Mnemonic Description 22 VCC_MIX Power Supply. Power supply voltage range is 4. 5.25 V. Each power supply pin should be decoupled with a 100 pF capacitor and a 0.1 μF capacitor located close to the ...
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TYPICAL PERFORMANCE CHARACTERISTICS RF FREQUENCY SWEEP CDAC = 0x0, internally generated high-side LO IP3SET = OPEN IP3SET = 3. –1 –2 –3 –4 –5 1410 1510 1610 1710 RF FREQUENCY (MHz) Figure 4. ...
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ADRF6602 IF FREQUENCY SWEEP CDAC = 0x0, internally generated swept low-side LO IP3SET = OPEN IP3SET = 3. –1 –2 –3 –4 – 100 125 150 175 200 225 250 ...
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IP3SET = OPEN –5 IP3SET = 3.3V –10 –15 –20 –25 –30 –35 –40 –45 –50 –55 –60 1550 1650 1750 1850 1950 LO FREQUENCY (MHz) Figure 14. LO-to-IF Feedthrough vs. LO Frequency, LO Output Turned Off, CDAC = ...
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ADRF6602 0 IP3SET = OPEN –5 IP3SET = 3.3V –10 –15 –20 –25 –30 –35 –40 –45 –50 –55 –60 1300 1500 1700 1900 RF FREQUENCY (MHz) Figure 20. RF-to-IF Leakage vs. RF Frequency, High-Side LO 140 MHz, ...
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Complementary cumulative distribution function (CCDF), f 100 IP3SET = OPEN IP3SET = 3. –1.5 –1.0 –0.5 0 0.5 1.0 GAIN (dB) Figure 26. Gain 100 IP3SET = OPEN IP3SET = ...
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ADRF6602 Measured at IF output, CDAC = 0x0, IP3SET = open, internally generated high-side LO −5 dBm 140 MHz, unless otherwise noted. Phase noise measurements made at LO output, unless otherwise noted –80 ...
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SPURIOUS PERFORMANCE (N × − (M × spur measurements were made using the standard evaluation board (see the Evaluation Board section). Mixer spurious RF LO products were measured in dB relative to the carrier (dBc) from ...
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ADRF6602 REGISTER STRUCTURE This section provides the register maps for the ADRF6602. The three LSBs determine the register that is programmed. REGISTER 0—INTEGER DIVIDE CONTROL (DEFAULT: 0x0001C0) RESERVED DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 ...
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REGISTER 2—FRACTIONAL DIVIDE CONTROL (DEFAULT: 0x001802) RESERVED DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 REGISTER 3—Σ-Δ MODULATOR DITHER CONTROL (DEFAULT: 0x10000B) DITHER DITHER MAGNITUDE ENABLE DB23 ...
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ADRF6602 REGISTER 4—PLL CHARGE PUMP, PFD, AND REFERENCE PATH CONTROL (DEFAULT: 0x0AA7E4) CP REF OUTPUT INPUT REF CURRENT MUX SELECT PATH REF SOURCE DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 RMS2 RMS1 ...
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REGISTER 5—PLL ENABLE AND LO PATH CONTROL (DEFAULT: 0x0000E5) RESERVED DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 REGISTER 6—VCO CONTROL AND VCO ENABLE (DEFAULT: ...
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ADRF6602 THEORY OF OPERATION The ADRF6602 integrates a high performance downconverting mixer with a state-of-the-art fractional-N PLL. The PLL also integrates a low noise VCO. The SPI port allows the user to control the fractional-N PLL functions and the mixer ...
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LO SELECTION LOGIC The downconverting mixer in the ADRF6602 can be used without the internal PLL by applying an external differential LO to Pin 37 and Pin 38 (LON and LOP). In addition, when using an LO generated by the ...
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ADRF6602 APPLICATIONS INFORMATION BASIC CONNECTIONS FOR OPERATION Figure 46 shows the schematic for the ADRF6602 evaluation board. The six power supply pins should be individually decoupled using 100 pF and 0.1 μF capacitors located as close as possible to the ...
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AC TEST FIXTURE Characterization data for the ADRF6602 was taken under very strict test conditions. All possible techniques were used to achieve optimum accuracy and to remove degrading effects of RF1 AGILENT N5181A HP 11636A POWER DIVIDER RF2 AGILENT N5181A ...
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ADRF6602 EVALUATION BOARD Figure 50 shows the schematic of the RoHS-compliant evaluation board for the ADRF6602. This board has four layers and was designed using Rogers 4350 hybrid material to minimize high frequency losses. FR4 material is also adequate if ...
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Figure 49. Main Screen of the ADRF6602 Evaluation Board Software Rev Page ADRF6602 ...
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ADRF6602 SCHEMATIC AND ARTWORK 0 R66 C28 10UF 0 VCC_BB R32 0 VCC_LO R31 0 VCC_RF R29 0 R33 0 0 R72 R62 3K R10 0 R37 TC4- R43 ...
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Figure 51. Evaluation Board Layout (Bottom) Figure 52. Evaluation Board Layout (Top) Rev Page ADRF6602 ...
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ADRF6602 EVALUATION BOARD CONFIGURATION OPTIONS Table 10. Component Description S1, R55, R56, R33 LO select. Switch and resistors to ground the LODRV_EN pin. The LODRV_EN pin setting, in combination with internal register settings, determines whether the LOP and LON pins ...
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... OUTLINE DIMENSIONS PIN 1 INDICATOR 12° MAX 1.00 0.85 0.80 SEATING PLANE ORDERING GUIDE 1 Model Temperature Range ADRF6602ACPZ-R7 −40°C to +85°C ADRF6602-EVALZ RoHS Compliant Part. 6.00 BSC SQ 0.60 MAX 0.50 TOP BSC 5.75 VIEW BSC SQ 0.50 0.40 0.30 0.80 MAX 0.65 TYP ...
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ADRF6602 NOTES Rev Page ...
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NOTES Rev Page ADRF6602 ...
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ADRF6602 NOTES ©2010 Analog Devices, Inc. All rights reserved. Trademarks and ©2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. registered trademarks are the property of their respective owners. D08545-0-9/10(C) D08545-0-9/10(C) ...