ADRF6602ACPZ-R7 Analog Devices Inc, ADRF6602ACPZ-R7 Datasheet - Page 21

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ADRF6602ACPZ-R7

Manufacturer Part Number
ADRF6602ACPZ-R7
Description
Manufacturer
Analog Devices Inc
Datasheet

Specifications of ADRF6602ACPZ-R7

Lead Free Status / Rohs Status
Compliant

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LO SELECTION LOGIC
The downconverting mixer in the ADRF6602 can be used
without the internal PLL by applying an external differential
LO to Pin 37 and Pin 38 (LON and LOP). In addition, when
using an LO generated by the internal PLL, the LO signal can
be accessed directly at these same pins. This function can be
used for debugging purposes, or the internally generated LO
can be used as the LO for a separate mixer.
Table 9. LO Selection Logic
Pin 16 (PLL_EN)
0
0
1
1
1
1
1
X = don’t care.
Pins
X
X
X
0
X
1
Pin 36 (LODRV_EN)
1
Bit DB6 (PLEN)
0
1
0
1
1
1
Rev. C | Page 21 of 32
Register 5 Bits
Bit DB3 (LDRV)
X
X
X
0
1
X
The operation of the LO generation and whether LOP and LON
are inputs or outputs are determined by the logic levels applied
at Pin 16 (PLL_EN) and Pin 36 (LODRV_EN), as well as Bit DB3
(LDRV) and Bit DB6 (PLEN) in Register 5. The combination of
externally applied logic and internal bits required for particular
LO functions is given in Table 9.
1
Output Buffer
Disabled
Disabled
Disabled
Disabled
Enabled
Enabled
Outputs
LO
External
External
External
Internal
Internal
Internal
ADRF6602

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