ADSP-21266SKBCZ-2B Analog Devices Inc, ADSP-21266SKBCZ-2B Datasheet - Page 16

• Manufacturer Part Number: ADSP-21266SKBCZ-2B
• Manufacturer: Analog Devices Inc

Specifications of ADSP-21266SKBCZ-2B

• Device Core Size: 32b
• Architecture: Super Harvard
• Format: Floating Point
• Clock Freq (max): 200MHz
• Mips: 200
• Device Input Clock Speed: 200MHz
• Ram Size: 256KB
• Program Memory Size: 512KB
• Operating Supply Voltage (typ): 1.2/3.3V
• Operating Supply Voltage (min): 1.14/3.13V
• Operating Supply Voltage (max): 1.26/3.47V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 136
• Lead Free Status / Rohs Status: Compliant

ADSP-21261/ADSP-21262/ADSP-21266
Voltage Controlled Oscillator
In application designs, the PLL multiplier value should be
selected in such a way that the VCO frequency never exceeds
f
The VCO frequency is calculated as follows:
f
f
where:
f
PLLM = Multiplier value programmed in the PMCTL register.
During reset, the PLLM value is derived from the ratio selected
using the CLK_CFG pins in hardware.
PLLD = 2, 4, 8, 16 based on the PLLD value programmed on the
PMCTL register. During reset this value is 1.
f
f
f
Note the definitions of various clock periods that are a function
of CLKIN and the appropriate ratio control shown in
and
VCO
VCO
CCLK
VCO
INPUT
INPUT
INPUT
• The product of CLKIN and PLLM must never exceed 1/2 of
• The product of CLKIN and PLLM must never exceed f
Table
f
(INDIV = 0).
(max) in
(INDIV = 1).
= 2 PLLM f
= VCO output
specified in
VCO
= (2 PLLM f
= is the input frequency to the PLL.
= CLKIN when the input divider is disabled or
= CLKIN 2 when the input divider is enabled
(max) in
14.
Table 16
RESET
XTAL
Table
Table 16
INPUT
INPUT
if the input divider is enabled
16.
BUF
CLKIN
) (2 PLLD)
4096 CLKIN
DELAY OF
if the input divider is not enabled
CYCLES
DIVIDER
PMCTL
CLKIN
PLLI
CLK
Figure 4. Core Clock and System Clock Relationship to CLKIN
RESETOUT
Rev. F | Page 16 of 44 | July 2009
Table 13
CLKOUT (TEST ONLY)
CLK_CFGx/PMCTL
VCO
FILTER
LOOP
MULTIPLIER
PLL
PLL
VCO
Table 13. CLKOUT and CCLK Clock Generation Operation
Table 14. Clock Periods
1
Figure 4
lator or crystal. The shaded divider/multiplier blocks denote
where clock ratios can be set through hardware or software
using the power management control register (PMCTL). For
more information, see the ADSP-2126x SHARC Processor
Peripherals Reference and Managing the Core PLL on Third-
Generation SHARC Processors (EE-290).
Timing
Requirements
CLKIN
CCLK
Timing
Requirements
t
t
t
t
t
where:
SR = serial port-to-core clock ratio (wide range, determined by SPORT
CK
CCLK
MCLK
SCLK
SPICLK
CLKDIV)
SPIR = SPI-to-core clock ratio (wide range, determined by SPIBAUD register)
SCLK = serial port clock
SPICLK = SPI clock
DIVIDER
shows core to CLKIN relationships with external oscil-
PLL
CLK_CFGx/
Core Clock
Description
Input Clock
PMCTL
Description
CLKIN Clock Period
(Processor) Core Clock Period
Internal memory clock = 1/2 t
Serial Port Clock Period = (t
SPI Clock Period = (t
PMCTL
DIVIDE
BY 2
BUF
1
Calculation
1/t
Variable, see equation
CK
CCLK
MCLK
CCLK
RESETOUT
CORERST
) × SPIR
CCLK
CCLK
) × SR