ADSP-21266SKBCZ-2B Analog Devices Inc, ADSP-21266SKBCZ-2B Datasheet - Page 36

• Manufacturer Part Number: ADSP-21266SKBCZ-2B
• Manufacturer: Analog Devices Inc

Specifications of ADSP-21266SKBCZ-2B

• Device Core Size: 32b
• Architecture: Super Harvard
• Format: Floating Point
• Clock Freq (max): 200MHz
• Mips: 200
• Device Input Clock Speed: 200MHz
• Ram Size: 256KB
• Program Memory Size: 512KB
• Operating Supply Voltage (typ): 1.2/3.3V
• Operating Supply Voltage (min): 1.14/3.13V
• Operating Supply Voltage (max): 1.26/3.47V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 136
• Lead Free Status / Rohs Status: Compliant

ADSP-21261/ADSP-21262/ADSP-21266
OUTPUT DRIVE CURRENTS
Figure 27
ers of the ADSP-2126x. The curves represent the current drive
capability of the output drivers as a function of output voltage.
TEST CONDITIONS
The ac signal specifications (timing parameters) appear in
Table 16 on Page 18
output disable time, output enable time, and capacitive loading.
Timing is measured on signals when they cross the 1.5 V level as
described in
sured between the point that the first signal reaches 1.5 V and
the point that the second signal reaches 1.5 V.
OUTPUT
–10
–20
–30
–40
PIN
Figure 28. Equivalent Device Loading for AC Measurements
40
30
20
10
TO
OUTPUT
Figure 29. Voltage Reference Levels for AC Measurements
0
INPUT
0
shows typical I-V characteristics for the output driv-
OR
Figure
V OL
0.5
1.5V
29. All delays (in nanoseconds) are mea-
3.47V, –45°C
SWEEP (V DDEXT ) VOLTAGE (V)
through
Figure 27. Typical Drive
1
(Includes All Fixtures)
3.11V, 125°C
30pF
1.5
Table 37 on Page
V OH
2
3.11V, 125°C
50
2.5
3.3V, 25°C
3
35. These include
3.3V, 25°C
3.47V, –45°C
1.5V
3.5
Rev. F | Page 36 of 44 | July 2009
1.5V
CAPACITIVE LOADING
Output delays and holds are based on standard capacitive loads:
30 pF on all pins (see
how output delays and holds vary with load capacitance (note
that this graph or derating does not apply to output disable
delays). The graphs of
not be linear outside the ranges shown for Typical Output Delay
vs. Load Capacitance and Typical Output Rise Time (20% to
80%, V = Min) vs. Load Capacitance.
12
10
0
8
6
4
2
12
10
4
8
6
2
0
0
0
Figure 31. Typical Output Rise/Fall Time
Figure 30. Typical Output Rise Time
y = 0.0467x + 1.6323
50
y = 0.049x + 1.5105
(20% to 80%, V
(20% to 80%, V
50
Figure
Figure
LOAD CAPACITANCE (pF)
LOAD CAPACITANCE (pF)
28).
100
30,
100
y = 0.0482x + 1.4604
y = 0.045x + 1.524
Figure 31
Figure
DDEXT
DDEXT
= Max)
= Min)
RISE
150
150
31, and
RISE
shows graphically
FALL
FALL
Figure 32
200
200
250
may
250