TDA7572 STMicroelectronics, TDA7572 Datasheet - Page 37

• Manufacturer Part Number: TDA7572
• Description: IC AMP PWM 200W BRIDGE 64HIQUAD
• Manufacturer: STMicroelectronics
• Type: Class Dr

Specifications of TDA7572

• Output Type: 1-Channel (Mono)
• Voltage - Supply: 8 V ~ 58 V
• Features: Digital Inputs, I²C, I²S, Mute, Short-Circuit and Thermal Protection, Standby
• Mounting Type: Surface Mount
• Package / Case: 64-HiQUAD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Max Output Power X Channels @ Load: -

TDA7572
6
6.1
6.2
Input stage and gain compressor
Input stage
The input stage accepts differential analog audio and provides a single ended output that is
referenced to SVR, a slowly changing reference signal that is close to V
present on the pin 6 (SVR). Four input stage gains are selectable, chosen such that input
signal levels of either 2V
output swing of this stage.
The variable gain is realized by a single ended input attenuator (with respect to SVR), such
that both differential and common-mode voltages are attenuated, and by, mean of a
reconfiguration of the Op-Amp feedback.
These are controlled by two bits, one controlling the input attenuator, and the other
controlling the Op-Amp configuration. The bits INLEVEL0 in the InputControl register
(register addr 1, bit 1) and INLEVEL1 in the Modulator register (register addr. 5, bit 2)
determine the gain selection. The default value of INLEVEL0 and INLEVEL1 bits are
determined by the voltage levels at power-up on pins PLL/INLEVEL0 (pin 63) pin and
SCL/INLEVEL1 (pin 62) respectively allowing gain selection without the requirement of an
I
of the feedback around the op. amp.
INP - pin 12
INM - pin 13
AOUT - pin 14
SCL/INLEVEL1 - pin62
PLL/INLEVEL0 - pin63
This stage is powered from ±2.5Volts, centered around SVR. Output swing is nominally ±2
volts. The input common mode range is a function of the gain setting, the electrical
parameters section must be consulted for details. It is expected that the inputs will be ac
coupled, and because of this consideration must be given to the rate of change of SVR, as
rapid changes to SVR could cause the inputs of this amplifier to run out of common mode
range. i.e. the input decoupling capacitors can not charge fast enough to keep up with SVR
Gain compressor
A gain compressor is integrated in the front end of this stage, which provides up to 16dB of
differential attenuation in approximately 0.5dB steps, varying somewhat depending on gain
configuration. Compressor aggressiveness is programmable by the I
(providing a choice from two attack-time/decay-time pairs) in non-I
bus with 2 bits each for attack and decay and 2 bits for the distortion-to-attenuation table.
These are bits ATTACK[1:0], DECAY[1:0], and TABLE[1:0] in the InputControl register. The
ADDR1/CompEnable pin is used in non-I
entirely.
The gain compressor operates by monitoring the estimated in THD due to clipping, over-
modulation or over-current and commanding a change in the input attenuation based on the
THD estimate. The input attenuator has 32 discrete steps. THD is estimated by measuring
the time period between zero crossings where there is no clipping and the time when there
2
C bus. INLEVEL0 controls the input attenuator, and INLEVEL1 controls the configuration
RMS
: positive input
: negative input
: output
: gain selection bit 1
: gain selection bit 0
, 2.6V
RMS
, 7V
2
C mode to enable or disable gain compression
RMS
, or 9.7V
RMS
Input stage and gain compressor
will provide full scale unclipped
2
C bus mode, or by I
2
C data/AttackSel pin
CC/2
. This signal is
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2
C