TDA7572 STMicroelectronics, TDA7572 Datasheet - Page 45

• Manufacturer Part Number: TDA7572
• Description: IC AMP PWM 200W BRIDGE 64HIQUAD
• Manufacturer: STMicroelectronics
• Type: Class Dr

Specifications of TDA7572

• Output Type: 1-Channel (Mono)
• Voltage - Supply: 8 V ~ 58 V
• Features: Digital Inputs, I²C, I²S, Mute, Short-Circuit and Thermal Protection, Standby
• Mounting Type: Surface Mount
• Package / Case: 64-HiQUAD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Max Output Power X Channels @ Load: -

TDA7572
In case of Fratio = "11" the configuration is still for full band. The input sample rate for this
case is 192kHz (Fs) and the first x4 interpolator has to be implemented off-line in the DSP.
For the first x2 interpolator could be used the precedent, for the second one should be used
the following:
Coefficients: -190, 1199,2047,…
To implement the first interpolator are necessary 28 memory access, 14 sum and14 MAC
(multiply with accumulation) at rate Fs. For the second one are, instead, enough 4 memory
access, 2 sum and 2 MAC at rate 2Fs. In the following schematic is reported the structure
for the two interpolator eventually to implement in the DSP.
Figure 8.
The I
Figure 9.
Where the WS is a clock at frequency Fs(48,96,192kHz) and discern which channel is
transferred, where the SCL is the interface clock at 64*Fs(3.07, 6.14, 12.29MHz). The SDA
are the bit transferred, 32 for each channel. Only the first 18 bits are taken into account and
only one channel. The Control register bit L/R selects the channel amplified.
The internal clock used to clock the DAC logic is obtained from the PLL that lock to the I2S
clock present on pin SCL. In order to work the PLL needs a RC series network connected to
pin PLL/INLEVEL0 (pin 44). Optimal value are C=100nF, R=33Ohm with in parallel an 1.8pF
capacitance
Oversampling
Filter
2
S format is used to transfer audio samples:
Type
Taps, bit
Attenuation 50db attenuation out of 0.77*(2Fs)
Coefficients It is an Half-Band filter then we have only 3
WS
SCL
SDA
Two interpolator structure diagram
I
2
S format diagram
32x18bit
RAM
MSB
Increasing word rate from 2Fs to 4Fs.
Remez filter, half band
7, 12
coefficients (see following)
LEFT
18
bit
18
bit
LSB
19
bit
16x12bit
ROM
MSB
12
bit
30
bit
RIGHT
LSB
REG
34
bit
AC00020
AC00021
MSB
45/64
DAC