10H20EV8-4F NXP Semiconductors, 10H20EV8-4F Datasheet

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10H20EV8-4F

Manufacturer Part Number
10H20EV8-4F
Description
Manufacturer
NXP Semiconductors
Datasheet

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10H20EV8-4F
Quantity:
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Philips Semiconductors Programmable Logic Devices
DESCRIPTION
The 10H20EV8/10020EV8 is an ultra
high-speed universal ECL PAL device.
Combining versatile output macrocells with a
standard AND/OR single programmable
array, this device is ideal in implementing a
user’s custom logic. The use of Philips
Semiconductors state-of-the-art bipolar oxide
isolation process enables the
10H20EV8/10020EV8 to achieve optimum
speed in any design. The SNAP design
software package from Philips
Semiconductors simplifies design entry
based upon Boolean or state equations.
The 10H20EV8/10020EV8 is a two-level logic
element comprised of 11 fixed inputs, an
input pin that can either be used as a clock or
12th input, 90 AND gates, and 8 Output Logic
Macrocells. Each Output Macrocell can be
individually configured as a dedicated input,
dedicated output with polarity control, a
bidirectional I/O, or as a registered output
that has both output polarity control and
feedback to the AND array. This gives the
part the capability of having up to 20 inputs
and eight outputs.
The 10H20EV8/10020EV8 has a variable
number of product terms that can be OR’d
per output. Four of the outputs have 12 AND
terms available and the other four have 8
terms per output. This allows the designer the
extra flexibility to implement those functions
that he couldn’t in a standard PAL device.
Asynchronous Preset and Reset product
terms are also included for system design
ease. Each output has a separate output
enable product term. Another feature added
for the system designer is a power-up Reset
on all registered outputs.
ORDERING INFORMATION
October 22, 1993
PAL is a registered trademark of Monolithic Memories, Inc., a wholly owned subsidiary of Advanced Micro Devices, Inc.
ECL programmable array logic
24-Pin Ceramic Dual In-Line (300mil-wide)
28-Pin Plastic Leaded Chip Carrier
DESCRIPTION
The 10H20EV8/10020EV8 also features the
ability to Preload the registers to any desired
state during testing. The Preload is not
affected by the pattern within the device, so
can be performed at any step in the testing
sequence. This permits full logical verification
even after the device has been patterned.
FEATURES
Ultra high speed ECL device
– t
– t
– t
– f
Universal ECL Programmable Array Logic
– 8 user programmable output macrocells
– Up to 20 inputs and 8 outputs
– Individual user programmable output
Variable product term distribution allows
increased design capability
Asynchronous Preset and Reset capability
10KH and 100K options
Power-up Reset and Preload function to
enhance state machine design and testing
Design support provided via SNAP and
other CAD tools
Security fuse for preventing design
duplication
Available in 24-Pin 300mil-wide DIP and
28-Pin PLCC.
polarity
PD
IS
CKO
MAX
= 2.6ns (max)
= 4.5ns (max)
= 2.3ns (max)
= 208MHz
ORDER CODE
10H20EV8–4F
10H20EV8–4A
10020EV8–4F
10020EV8–4A
113
PIN CONFIGURATIONS
V
F = Ceramic DIP (300mil-wide)
A = Plastic Leaded Chip Carrier
CO1
10H20EV8/10020EV8
NC
F
F
F
F
I
1
2
3
4
3
CLK/I
CLK/I
10
11
5
6
7
8
9
V
CO1
V
EE
12
I
DRAWING NUMBER
F
F
F
F
4
12
4
12
I
I
I
I
I
1
2
3
4
1
2
3
4
5
10
11
12
13 14
I
I
1
2
3
4
5
6
7
8
9
3
2
5
A Package
F Package
V
EE
I
0586B
0401F
2
1
NC
NC
15
1
Product specification
V
28
16 17 18
CC
I
6
853–1423 11164
I
27
11
I
7
24
23
22
21
20
19
18
17
16
15
14
13
I
26
10
I
8
V
I
I
F
F
V
F
F
I
I
I
I
11
10
9
8
7
6
8
7
6
5
CC
CO2
25
24
23
22
21
20
19
F
F
V
NC
F
F
I
9
8
7
CO2
6
5

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10H20EV8-4F Summary of contents

Page 1

... The SNAP design software package from Philips Semiconductors simplifies design entry based upon Boolean or state equations. The 10H20EV8/10020EV8 is a two-level logic element comprised of 11 fixed inputs, an input pin that can either be used as a clock or 12th input, 90 AND gates, and 8 Output Logic Macrocells ...

Page 2

... NOTES: 1. All unprogrammed or virgin “AND” gate locations are pulled to logic “0” 2. Programmable connections 3. Pinout for F Package October 22, 1993 INPUT LINES 114 Product specification 10H20EV8/10020EV8 OUTPUT 4 LOGIC MACRO CELL OUTPUT 21 LOGIC MACRO CELL OUTPUT 5 LOGIC MACRO CELL OUTPUT 20 LOGIC ...

Page 3

... Output Logic Macrocell The 10H20EV8/10020EV8 incorporates an extremely versatile Output Logic Macrocell that allows the user complete flexibility when configuring outputs. As seen in Figure 1, the 10H20EV8/ 10020EV8 Output Logic Macrocell consists of an edge-triggered D-type flip-flop, an output select MUX, and a feedback select MUX. Fuses S ...

Page 4

... Storage Temperature range J NOTE: 1. Stresses above those listed may cause malfunction or permanent damage to the device. This is a stress rating only. Functional operation at these or any other condition above those indicated in the operational and programming specification of the device is not implied. DC OPERATING CONDITIONS 10H20EV8 SYMBOL PARAMETER ...

Page 5

... LOW, even though the Q output of all flip-flops would go HIGH. A Reset signal would force the opposite conditions. PRELOAD To simplify testing, the 10H20EV8/10020EV8 has also included PRELOAD circuitry. This allows a user to load any particular data desired into the registers regardless of the programmed pattern. This means that the ...

Page 6

... Philips Semiconductors Programmable Logic Devices ECL programmable array logic DC ELECTRICAL CHARACTERISTICS 10H20EV8 + –5.2V 5 amb SYMBOL PARAMETER V High level output voltage OH V Low level output voltage OL I High level input current IH I Low level input current IL –I Supply current EE DC ELECTRICAL CHARACTERISTICS 10020EV8 ...

Page 7

... Philips Semiconductors Programmable Logic Devices ECL programmable array logic AC ELECTRICAL CHARACTERISTICS (for Ceramic Dual In-Line Package) 10H20EV8 + –5.2V amb EE 10020EV8 +85 C, –4.8V V amb EE SYMBOL PARAMETER FROM Pulse Width t Clock High CLK + CKH t Clock Low CLK – CKL t Clock Period CLK + CKP ...

Page 8

... Philips Semiconductors Programmable Logic Devices ECL programmable array logic AC ELECTRICAL CHARACTERISTICS (for Plastic Leaded Chip Carrier) 10H20EV8 + –5.2V amb EE 10020EV8 +85 C, –4.8V V amb EE SYMBOL PARAMETER FROM Pulse Width t Clock High CLK + CKH t Clock Low CLK – CKL t Clock Period CLK + CKP ...

Page 9

... CLK 0.01 F –2.5V + 0.010V FOR 10020EV8 –3.2V + 0.010V FOR 10H20EV8 , and 0.01 F and 25 F from GND the distance from the DUT pin to the junction of the cable from the Pulse inch (6mm inch (6mm) in length (refer to section on AC setup procedure better. 121 ...

Page 10

... CO1 CO2 AMPLITUDE REP RATE PULSE WIDTH TLH 740mV 1MHz 500ns 0.7 + 0.1ns P–P Input Pulse Definition 122 Product specification 10H20EV8/10020EV8 +1110mV (10H20EV8) +1050mV (10020EV8) +310mV +1110mV (10H20EV8) +1050mV (10020EV8) +310mV = GND (0V) t THL 1.3 + 0.2ns = GND (0V) t THL 0.7 + 0.1ns ...

Page 11

... TIMING DIAGRAMS I, I/O 50% (INPUT) CLK I/O (REGISTERED OUTPUT) I/O (COMBINATORIAL OUTPUT) 0V REGISTERED ACTIVE-LOW OUTPUT I, I/O (INPUT) October 22, 1993 50 50% 50% t CKH CKO P 50 50% Flip-Flop and Gate Outputs V = –4.94 10H20EV8 –4.2 10020EV8 PPR 50 CLK 50% 50% Power-On Reset 123 Product specification 10H20EV8/10020EV8 50% t CKL ...

Page 12

... Philips Semiconductors Programmable Logic Devices ECL programmable array logic TIMING DIAGRAMS (Continued) I, I/O 50% (INPUT) I/O (OUTPUT) CLK ASYNCHRONOUS PRESET/RESET I/O (OUTPUT) October 22, 1993 t OD 50% Output Enable/Disable 50% t PRH t PRO 50% Asynchronous Preset/Reset 124 Product specification 10H20EV8/10020EV8 50 50% 50% t PRS 50% ...

Page 13

... Philips Semiconductors Programmable Logic Devices ECL programmable array logic REGISTER PRELOAD The 10H20EV8/10020EV8 has included circuitry that allows a user to load data into the output registers. Register PRELOAD can be done at any time and is not dependent on any particular pattern programmed into the device. This simplifies the ability to fully verify logic states and sequences even after the device has been patterned ...

Page 14

... CUPL is a trademark of Logical Devices, Inc. October 22, 1993 All packages allow Boolean and state equation entry formats. SNAP, ABEL and CUPL also accept, as input, schematic capture format. 10H20EV8/10020EV8 logic designs can also be generated using the program table entry format detailed on the following page. This ...

Page 15

... Philips Semiconductors Programmable Logic Devices ECL programmable array logic PROGRAM TABLE T AND PIN October 22, 1993 CONTROL WORD POLARITY OR (FIXED) F(I) F( 127 Product specification 10H20EV8/10020EV8 ...

Page 16

... PS/2, or any compatible system with DOS 2.1 or higher. A minimum of 640K bytes of RAM is required together with a hard disk. DESIGN SECURITY The 10H20EV8/10020EV8 has a programmable security fuse that controls the access to the data programmed in the device. By using this programmable feature, proprietary designs implemented in the ...

Page 17

... LOGIC MACROCELL MACROCELL MACROCELL OUTEV8 OUTEV8 OUTEV8 OUTPUT OLMREG SELECT MUX S S CLK FEEDBACK MUX Output Logic Macrocell 129 Product specification 10H20EV8/10020EV8 I 11 NINEV8 DINEV8 AND OUTPUT OUTPUT LOGIC LOGIC PRESET MACROCELL MACROCELL OUTEV8 OUTEV8 OUTEV8 OUTEV8 F n OLMDIR V CC OLMINV ...

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