UPD3768D NEC, UPD3768D Datasheet

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UPD3768D

Manufacturer Part Number
UPD3768D
Description
7500 PIXELS x 3 COLOR CCD LINEAR IMAGE SENSOR
Manufacturer
NEC
Datasheet
Document No. S15418EJ2V0DS00 (2nd edition)
Date Published September 2002 NS CP (K)
Printed in Japan
DESCRIPTION
changes optical images to electrical signal and has the function of color separation.
transfer register, which transfers the photo signal electrons of 7500 pixels separately in odd and even pixels.
Therefore, it is suitable for 600 dpi/A3 high-speed color digital copiers, color scanners and so on.
FEATURES
• Valid photocell
• Photocell pitch
• Line spacing
• Color filter
• Resolution
• Drive clock level : CMOS output under 5 V operation
• Data rate
• Output type
• Power supply
• On-chip circuits : Reset feed-through level clamp circuits
ORDERING INFORMATION
The µ PD3768 is a high-speed and high sensitive color CCD (Charge Coupled Device) linear image sensor which
The µ PD3768 has 3 rows of 7500 pixels, and it is a 2-output/color type CCD sensor with 2 rows/color of charge
Part Number
µ PD3768D
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
7500 PIXELS × × × × 3 COLOR CCD LINEAR IMAGE SENSOR
: 7500 pixels × 3
: 9.325 µ m
: 37.3 µ m (4 lines) Red line - Green line, Green line - Blue line
: Primary colors (red, green and blue), pigment filter (with light resistance 10
: 24 dot/mm A3 (297 × 420 mm) size (shorter side)
: 44 MHz MAX. (22 MHz/1 output)
: 2 outputs in phase/color
: +10 V
Voltage amplifiers
CCD linear image sensor 36-pin ceramic DIP (CERDIP) (15.24 mm (600))
The mark
DATA SHEET
shows major revised points.
Package
MOS INTEGRATED CIRCUIT
µ µ µ µ PD3768
7
lx•hour)
2001

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UPD3768D Summary of contents

Page 1

... CCD linear image sensor 36-pin ceramic DIP (CERDIP) (15.24 mm (600)) The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. S15418EJ2V0DS00 (2nd edition) ...

Page 2

BLOCK DIAGRAM φ φ OUT 32 (Blue, even) GND OUT 34 (Blue, odd) GND OUT 36 (Green, odd OUT 1 (Green, even) GND ...

Page 3

... Last stage shift register clock Shift register clock 10 No connection No connection No connection Shift register clock 1A Shift register clock 2B Transfer gate clock 3 (for Red) Ground No connection No connection Caution Connect the No connection pins (NC) to GND. PHOTOCELL STRUCTURE DIAGRAM µ m 6.325 3 µ m Channel stopper Aluminum shield V ...

Page 4

ABSOLUTE MAXIMUM RATINGS (T Parameter Output drain voltage V OD Shift register clock voltage V φ 1 Last gate shift register clock voltage V φ 2L Reset gate clock voltage V φ R Clamp clock voltage V φ CP Transfer ...

Page 5

ELECTRICAL CHARACTERISTICS = +25° MHz, data rate = 2 MHz, storage time = 10 ms, input signal clock = 5 V φ light source (except Response1) : 2950 K ...

Page 6

C, V INPUT PIN CAPACITANCE (T A Parameter Shift register clock pin capacitance Last stage shift register clock pin capacitance Reset gate clock pin capacitance Clamp clock pin capacitance Transfer gate ...

Page 7

TIMING CHART 1 (Bit clamp mode, for each color) φ φ TG1 to TG3 φ φ φ 10, 1A, 1B φ φ φ 20, 2A, 2B φ 2L φ R φ CP Note OUT V 2, ...

Page 8

TIMING CHART 2 (Bit clamp mode, for each color) φ φ φ 10, 1A, 1B φ φ φ 20, 2A, 2B t7L 90% φ 90% φ R 10% t16 90% φ ...

Page 9

TIMING CHART 3 (Line clamp mode, for each color) φ φ TG1 to TG3 φ φ φ 10, 1A, 1B φ φ φ 20, 2A, 2B φ 2L φ R φ CP Note OUT V 2, ...

Page 10

TIMING CHART 4 (Line clamp mode, for each color) φ φ φ 10, 1A, 1B φ φ φ 20, 2A, 2B t7L 90% φ 90% φ R 10% φ ...

Page 11

TIMING CHART 5 (Bit clamp mode, line clamp mode, for each color) t2 90% φ φ TG1 to TG3 10% t1 90% φ φ φ 10, 1A, 1B φ φ φ 20, 2A, 2B φ 2L φ R φ CP ...

Page 12

φ φ φ φ 10, φ φ φ φ 20 cross points φ 10 φ 20 φ φ φ φ 1A, φ φ φ φ 2A cross points φ 1A φ 2A φ φ φ φ 1B, φ φ φ ...

Page 13

DEFINITIONS OF CHARACTERISTIC ITEMS 1. Saturation voltage : V sat Output signal voltage at which the response linearity is lost. 2. Saturation exposure : SE Product of intensity of illumination (lx) and storage time (s) when saturation of output voltage ...

Page 14

Dark signal non-uniformity : DSNU Absolute maximum of the difference between ADS and voltage of the highest or lowest output pixel of all the valid pixels at light shielding. This is calculated by the following formula, and it is ...

Page 15

Image lag O/E : IL-O defined as a difference of the average of image lag of odd and even pixels for each color. 11. Register imbalance : RI The rate of the difference between the averages of ...

Page 16

STANDARD CHARACTERISTIC CURVES (Reference Value) DARK OUTPUT TEMPERATURE CHARACTERISTIC 0.5 0.25 0 Operating Ambient Temperature T TOTAL SPECTRAL RESPONSE CHARACTERISTICS (without infrared cut filter and heat absorbing filter) (T 100 80 ...

Page 17

... TG3 Caution Connect the No connection pins (NC) to GND. Remarks 1. Connect two inverters (74AC04) to each φ 10, φ 1A, φ 1B, φ 20, φ 2A, φ 2B pin. 2. Inverters shown in the above application circuit example are the 74AC04 the application circuit example are shown in the figure below. ...

Page 18

PACKAGE DRAWING CCD LINEAR IMAGE SENSOR 36-PIN CERAMIC DIP (15.24 mm (600)) 94.0±0.7 3.0±0.1 1.28±0.1 26.0±0.2 1 33.3±0.6 The 1st valid pixel 24.13±0.20 20.32±0.13 48.26±0.40 18 3.00±0.08 1.0±0.08 7.33±0.3 (5.0) 1.27 0.46 20.32±0.13 2.54±0.13 2.0±0.2 5.0±0.2 Name Dimension Glass cap ...

Page 19

RECOMMENDED SOLDERING CONDITIONS When soldering this product highly recommended to observe the conditions as shown below. If other soldering processes are used the soldering is performed under different conditions, please make sure to consult with our ...

Page 20

NOTES ON HANDLING THE PACKAGES 1 MOUNTING OF THE PACKAGE The application of an excessive load to the package may cause the package to warp or break, or cause chips to come off internally. Particular care should be taken when ...

Page 21

... Anyone who is handling CCD image sensors, mounting them on PCBs or testing or inspecting PCBs on which CCD image sensors have been mounted must wear anti-static bands such as wrist straps and ankle straps which are grounded via a series resistance connection of about 1 MΩ. Data Sheet S15418EJ2V0DS µ ...

Page 22

Data Sheet S15418EJ2V0DS µ µ µ µ PD3768 ...

Page 23

... HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction connection is provided to the input pins possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry ...

Page 24

... NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC or others. • ...

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