UPD3788D NEC, UPD3788D Datasheet
UPD3788D
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UPD3788D Summary of contents
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... CCD linear image sensor 36-pin ceramic DIP (15.24 mm (600)) The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. S14664EJ1V0DS00(1st edition) ...
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COMPARISON CHART Item ABSOLUTE MAXIMUM Shift register clock voltage (V) RATINGS Reset gate clock voltage (V) Reset feed-through level clamp clock voltage (V) Transfer gate clock voltage (V) ELECTRICAL Saturation exposure (Ix·s) CHARACTERISTICS Response (V/Ix·s) Response peak (nm) Random noise ...
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BLOCK DIAGRAM CLB GND V 2 OUT 32 (Blue, even) GND OUT 34 (Blue, odd) GND OUT 36 (Green, odd OUT 1 (Green, even) GND ...
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... GND 6 31 GND Reset feed-through level CLB OD clamp clock Last stage shift register clock Shift register clock connection connection connection Shift register clock Shift register clock 1 TG3 TG1 Transfer gate clock 1 (for Blue GND 16 21 TG2 Transfer gate clock 2 (for Green ...
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ABSOLUTE MAXIMUM RATINGS (T Parameter Output drain voltage Shift register clock voltage Reset gate clock voltage Reset feed-through level clamp clock voltage Transfer gate clock voltage Operating ambient temperature Storage temperature Caution Exposure to ABSOLUTE MAXIMUM RATINGS for extended periods ...
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ELECTRICAL CHARACTERISTICS MHz, data rate = 2 MHz, storage time = 10 ms, input signal clock = light source: 3200 K halogen lamp +C-500S ...
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... Last stage shift register clock pin capacitance Reset gate clock pin capacitance Reset feed-through level clamp clock pin capacitance Transfer gate clock pin capacitance Remark Pins 13 and pin 9 ( 10) are connected each other inside of the device. Pins 14 and pin 28 ( 20) are connected each other inside of the device Symbol Pin name Pin No ...
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TIMING CHART 1 (Bit clamp mode, for each color) TG1 to TG3 CLB Note OUT OUT Note Input the RB and CLB pulses continuously ...
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TIMING CHART 2 (Bit clamp mode, for each color 10 20 CLB OUT V 6 OUT Symbol t1, t2 t1’, t2’ t5, t6 ...
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Notes 1. MIN. of t10 shows that the RB and CLB overlap each other. RB CLB 2. MIN. of t11 shows that the 1L and CLB overlap each other. 1L CLB t10 t11 ...
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TIMING CHART 3 (Bit clamp mode, for each color) TG1 to TG3 CLB Symbol t11 t12 t13, t14 t15, t16 Notes 1. Input the RB and CLB pulses continuously during this period, ...
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TIMING CHART 4 (Line clamp mode, for each color) TG1 to TG3 CLB Note OUT OUT Note Set the RB to high level during ...
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TIMING CHART 5 (Line clamp mode, for each color 10 20 t1' RB “H” CLB OUT V 6 OUT Symbol t1, t2 t1’, t2’ t5, ...
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TIMING CHART 6 (Line clamp mode, for each color) TG1 to TG3 CLB Symbol t12 t13, t14 t15, t16 t17, t18 t19 t20, t21 Note Set the RB to high ...
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DEFINITIONS OF CHARACTERISTIC ITEMS 1. Saturation voltage: V sat Output signal voltage at which the response linearity is lost. 2. Saturation exposure: SE Product of intensity of illumination (I 3. Photo response non-uniformity: PRNU The output signal non-uniformity of all ...
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Dark signal non-uniformity: DSNU Absolute maximum of the difference between ADS and voltage of the highest or lowest output pixel of all the valid pixels at light shielding. This is calculated by the following formula. DSNU (mV) : maximum ...
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Register imbalance: RI The rate of the difference between the averages of the output voltage of Odd and Even pixels, against the average output voltage of all the valid pixels – – ...
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STANDARD CHARACTERISTIC CURVES (Nominal) DARK OUTPUT TEMPERATURE CHARACTERISTIC 0.5 0.25 0 Operating Ambient Temperature T TOTAL SPECTRAL RESPONSE CHARACTERISTICS (without infrared cut filter and heat absorbing filter 100 80 ...
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APPLICATION CIRCUIT EXAMPLE + F/ Remarks 1. Pin 9 ( 10) and pin 28 ( 20) should be open to decrease the influence of input clock noise ...
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EQUIVALENT CIRCUIT CCD V OUT 0.1 F 4.7 k 110 2SC945 47 2SA1005 1 k Data Sheet S14664EJ1V0DS00 PD3788 ...
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PACKAGE DRAWING CCD LINEAR IMAGE SENSOR 36-PIN CERAMIC DIP (15.24mm (600)) (Unit : mm) 94.00 0.50 1 9.5 0.9 2 (35.0) The 1st valid pixel 88.9 0.6 1 The 1st valid pixel 2 The 1st valid pixel 3 The surface ...
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NOTES ON THE USE OF THE PACKAGE The application of an excessive load to the package may cause the package to warp or break, or cause chips to come off internally. Particular care should be taken when mounting the package ...
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... HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction connection is provided to the input pins possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry ...
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... NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC or others ...