W741E201 Information Storage Devices, Inc, W741E201 Datasheet
W741E201
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W741E201 Summary of contents
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Table of Contents-- GENERAL DESCRIPTION ......................................................................................................................... 2 FEATURES................................................................................................................................................. 2 PIN CONFIGURATIONS ............................................................................................................................ 3 PIN DESCRIPTION .................................................................................................................................... 4 BLOCK DIAGRAM...................................................................................................................................... 5 FUNCTIONAL DESCRIPTION ................................................................................................................... 6 ABSOLUTE MAXIMUM RATINGS ............................................................................................................. 28 DC CHARACTERISTICS............................................................................................................................ 29 AC CHARACTERISTICS............................................................................................................................ 30 PAD ASSIGNMENT & POSITIONS............................................................................................................ 31 ...
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GENERAL DESCRIPTION The W741E20X is a high-performance 4-bit microcontroller (µC) that provides an flash EEPROM for the program memory. The device contains a 4-bit ALU, two 8-bit timers, a divider, a serial port, and five 4-bit I/O ports (including 3 ...
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... One serial transmission/receiver port specified by software • µS instruction cycle (with 4 MHz operating frequency) • Packaged in 18-pin, 20-pin, 28-pin PDIP and 20-pin, 28-pin SOP • PIN CONFIGURATIONS W741E201 RA2 1 (DATA) RA3 2 (MODE) /INT 3 (Vpp) /RES 4 VSS 5 RB0 6 RB1 7 RB2 8 RB3 9 18-PDIP (300 mil) ...
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PIN DESCRIPTION SYMBOL I/O XIN I Input pin for oscillator. Connected to crystal or resistor to generate system clock by code option. XOUT O Output pin for oscillator. Connected to crystal or resistor to generate system clock by code option. ...
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BLOCK DIAGRAM RAM (128*4) Flash VPP (RES) EEPROM DATA (RA3) (2048*16) (look_up table MODE (INT) 2K*4) +1(+2) PC STACK (8 Levels) Timer 0 (8-bit) Watchdog Timer (4-bit) Preliminary W741E20X PORT RA ACC PORT RB ALU PORT RC Central Control PORT ...
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FUNCTIONAL DESCRIPTION Program Counter (PC) Organized as an 11-bit binary counter (PC0 to PC10), the program counter generates the addresses of the 2048 × 16 on-chip flash EEPROM containing the program instruction. When the jump or subroutine call instructions or ...
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Data Memory (RAM) 1. Architecture The static data memory (RAM) used to store data is arranged as 128 × 4 bits. The data memory can be addressed directly or indirectly. The organization of the data ...
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The first sixteen addresses (00H to 0FH) in the data memory are known as the working registers (WR). The other data memory is used as general memory and cannot operate directly with immediate data. The relationship between data memory locations ...
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Clock Generator The W741E20X provides a crystal or RC oscillation circuit selected by option codes to generate the system clock through external connections crystal oscillator is used, a crystal or a ceramic resonator must be connected to XIN ...
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Divider0 Fosc ... Q10 Q11 Q12 PMF.3 Fosc/16384 Fosc/1024 Figure 4. Organization of Divider and Watchdog Timer Parameter Flag (PMF) The parameter flag is organized as a 4-bit binary register (PMF.0 to PMF.3). The PMF is controlled ...
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Timer/Counter Timer 0 (TM0) Timer 0 (TM0 programmable 8-bit binary down-counter. The specified value can be loaded into TM0 by executing the MOV TM0L(TM0H MOV TM0, #I instruction. When the MOV TM0L (TM0H), R instructions are ...
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The source can be selected by setting bit 0 and bit 1 of mode register 1 (MR1). At initial reset, the Timer 1 clock input is Fosc external clock is selected as the clock source of ...
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For example, when F equals 32768 Hz, depending on the preset value of TM1, the MFP pin will T output a single tone signal in the tone frequency range from 16384 Hz. The relation between the tone ...
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Mode Register 1 (MR1) Mode Register 1 is organized as a 4-bit binary register (MR1.0 to MR1.3). MR1 can be used to control the operation of Timer 1. The bit descriptions are as follows: 3 MR1 W Note: W means ...
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Port Mode 0 Register (PM0) The port mode 0 register is organized as 4-bit binary register (PM0.0 to PM0.3). PM0 can be used to determine the structure of the input/output ports controlled by the MOV PM0, #I instruction. ...
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Bit RB.0 works as output pin; Bit RB.0 works as input pin Bit RB.1 works as output pin; Bit RB.1 works as input pin Bit ...
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Bit RC.0 works as output pin; Bit RC.0 works as input pin Bit RC.1 works as output pin; Bit RC.1 works as input pin Bit ...
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Input/Output Pin of the RC(RD) Output Buffer Enable DATA BUS MOV RC, R (or MOV RD, R) Instruction Figure 9. Architecture of RC & RD Input/Output Pins Port Enable Flag (PEF) The port enable flag is organized as 4-bit binary ...
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Bit Signal change at RC.0 Bit Signal change at RC.1 Bit Signal change at RC.2 Bit Signal change at RC.3 DATA BUS RC.0 Signal change detector RC.1 Signal ...
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Output Port RE Output port RE can be used as an output of the internal RT port serial input/output port. The control flow is shown in Figure 8. When bit 1 of port mode 3 register (PM3) ...
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When the SOP R instruction is executed, the data will be loaded to the serial output buffer (SOB) and bit 3 of port status register 2 will be set to "1" (BUSYO = 1). Then the CLKO pin will ...
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Bit 0 is reserved. Bit 1 (BUSYI): Serial port input busy flag. Bit 2 is reserved. Bit 3 (BUSYO): Serial port output busy flag. MFP Output Pin (MFP) The MFP output pin can output the Timer 1 clock or the ...
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Continued Interrupts The W741E20X provides five internal interrupt sources (Divider 0, Timer 0, Timer 1, serial I/O) and two external ...
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Interrupt Enable Flag (IEF) The interrupt enable flag is organized as an 8-bit binary register (IEF.0 to IEF.7). These bits are used to control the interrupt conditions controlled by the MOV IEF, #I instruction. When one of these ...
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SEF Device will exit stop mode when falling edge signal is applied to pin RC.1 SEF Device will exit stop mode when falling edge signal is applied to pin RC.2 SEF ...
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Hold Mode Release Enable Flag (HEF) The hold mode release enable flag is organized as an 8-bit binary register (HEF.0 to HEF.7). The HEF is used to control the hold mode release conditions controlled by the MOV HEF, ...
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Event Flag (EVF) The event flag is organized as a 8-bit binary register (EVF0 to EVF7 set by hardware and reset by CLR EVF, #I instruction or the occurrence of an interrupt. The bit descriptions are as follows: ...
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EEPROM Program/Erase Description The built-in program code memory of the W741E20X is the EEPROM structure. This memory can be programmed, erased and verified through the VPP, MODE and DATA pins. The on board program/erase connection is shown below. XTAL 26 ...
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DC CHARACTERISTICS (VDD-VSS = 3.0 V, Fosc. = 32.768 KHz ° C; unless otherwise specified) PARAMETER Op. Voltage Op. Current (Crystal type) Op. Current (RC type) Hold Current (Crystal type) Hold Current (RC type) Stop Current (Crystal ...
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AC CHARACTERISTICS (VDD-VSS = 3 ° C; unless otherwise specified) PARAMETER Op. Frequency Frequency Deviation by Voltage Drop for RC Oscillator Instruction Cycle Time Serial Port Data Ready Time Serial Port Data Hold Time Reset Active ...
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PAD ASSIGNMENT & POSITIONS Note: The chip substrate must be connected to system ground (V PAD NO. PAD NAME 1 RA2 -207.80 2 RA3 -482.00 3 -804.20 INT 4 -1160.80 RES 5 V -1160. RE0 -1158.80 7 RE1 ...
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TYPICAL APPLICATION CIRCUIT Output Signal Vcc Vcc or Preliminary W741E20X Vcc V DD RA0 RA3 Vcc RB0 RB1 RB2 RB3 RD0 RC0 RD1 RC1 RD2 RC2 RC3 RD3 INT RE0 RES RE1 RE2 XOUT RE3 MFP XIN ...
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INSTRUCTION SET TABLE Symbol Description ACC: Accumulator ACC.n: Accumulator bit n WR: Working Register PAGE: Page Register MR0: Mode Register 0 MR1: Mode Register 1 PM0: Port Mode 0 PM1: Port Mode 1 PM2: Port Mode 2 PM3: Port Mode ...
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Continued ! =: Not equal &: AND ^: OR EX: Exclusive OR Transfer direction, result ← : [PAGE*10H+()]: Contents of address PAGE (bit2, bit1, bit0)*10H+() [P()]: Contents of port P INSTRUCTION SET TABLE 1 MNEMONIC Arithmetic ADD R, ACC ACC ...
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Instruction Set Table 1, continued MNEMONIC Arithmetic INC R ACC, R ← ( DEC R ACC, R ← ( Logic Operations ANL R, ACC ACC ← (R) & (ACC) ANL WR, #I ACC ← (WR) & ...
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Instruction Set Table 1, continued MNEMONIC Data Move MOV WR ← (R) MOV ← (WR) MOVA WR, R ACC, WR ← (R) MOVA R, WR ACC, R ← (WR) MOV R, ACC R ← (ACC) ...
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Instruction Set Table 1, continued MNEMONIC MOVA R, HCFL ACC, R ← HCF0 − HCF3 MOVA R, HCFH ACC, R ← HCF4 − HCF7 CLR PMF, #I Clear Parameter Flag SET PMF, #I Set Parameter Flag ...
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Instruction Set Table 1, continued MNEMONIC Timer MOV TM0L, R TM0L ← (R) MOV TM0H, R TM0H ← (R) MOV TM0, #I Timer 0 set MOV TM1L, R TM1L ← (R) MOV TM0H, R TM0H ← (R) MOV TM1, #I ...
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INSTRUCTION SET TABLE 2 ADC R, ACC Add R to ACC with CF Machine Code: 0 Machine Cycle: 1 ACC ← (R) + (ACC) + (CF) Operation: The contents of the data memory location addressed R0, ACC, ...
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Instruction Set Table 2, continued ADCR WR, #I Add immediate data to WR with CF Machine Code: 0 Machine Cycle: 1 Operation: ACC, WR ← (WR (CF) Description: The contents of the Working Register (WR ...
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Instruction Set Table 2, continued ADDR R, ACC Add R to ACC Machine Code Machine Cycle: ACC, R ← (R) + (ACC) Operation: The contents of the data memory location addressed and ACC Description: ...
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Instruction Set Table 2, continued ADU WR, #I Add immediate data to WR and Carry Flag unchange Machine Code Machine Cycle: ACC ← (WR Operation: The contents of the Working Register (WR) and the immediate data ...
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Instruction Set Table 2, continued ANL R, ACC And R to ACC Machine Code: 0 Machine Cycle: 1 Operation: ACC ← (R) & (ACC) Description: The contents of the data memory location addressed and the ACC ...
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Instruction set table 2, continued ANLR WR, #I And immediate data to WR Machine Code: 0 Machine Cycle: 1 Operation: ACC, WR ← (WR) & I Description: The contents of the Working Register (WR) and the immediate data I are ...
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Instruction Set Table 2, continued CLR DIVR0 Reset the last 4 bits of the DIVideR 0 Machine Code: 0 Machine Cycle: 1 Operation: Reset the last 4 bits of the divider 0 Description: When this instruction is executed, the last ...
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Instruction Set Table 2, continued CLR PMF, #I Clear ParaMeter Flag 0 Machine Code: Machine Cycle: 1 Operation: Clear Parameter Flag Description: Description of each flag: I0, I1, I2: Reserved The input clock of the watchdog timer ...
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Instruction Set Table 2, continued DEC R Decrement R content 0 Machine Code: Machine Cycle: 1 Operation: ACC, R ← ( Description: Decrement the data memory content and load result into the ACC and the data memory. Flag ...
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Instruction Set Table 2, continued DSKZ R Decrement R content then skip if ACC is zero Machine Code: 0 Machine Cycle: 1 Operation: ACC, R ← ( ← (PC ACC = 0 Description: Decrement ...
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Instruction Set Table 2, continued INC R Increment R content 0 Machine Code: Machine Cycle: 1 Operation: ACC, R ← ( Description: Increment the data memory content and load the result into the ACC and the data memory. ...
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Instruction Set Table 2, continued JB2 L Jump when bit 2 of ACC is "1" 1 Machine Code: Machine Cycle: 1 Operation: PC10 ~ PC0 ← L10 ~ L0; if ACC.2="1" Description: If bit 2 of the ACC is "1," ...
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Instruction Set Table 2, continued JNC L Jump when CF is not "1" Machine Code: 1 Machine Cycle: 1 Operation: PC10 ~ PC0 ← L10 ~ L0 "0" Description "0," PC10 to PC0 of ...
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Instruction Set Table 2, continued MOV ACC, R Move R content to ACC Machine Code: 0 Machine Cycle: 1 Operation: ACC ← (R) Description: The contents of the data memory location addressed are loaded into the ...
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Instruction Set Table 2, continued MOV HEF, #I Set/Reset Hold mode release Enable Flag 0 Machine Code: 1 Machine Cycle: Hold mode release enable flag control Operation: Description: I0~ ...
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Instruction Set Table 2, continued I0~ MOV MFP, #I Modulation Frequency Pulse generator 0 Machine Code: 1 Machine ...
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Instruction Set Table 2, continued MOV MR0, #I Load immediate data to Mode Register 0 (MR0) Machine Code: 0 Machine Cycle: 1 Operation: MR0 ← I Description: The immediate data I are loaded to the MR0. MR0 bits description: bit ...
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Instruction Set Table 2, continued MOV PAGE, #I Load immediate data to Page Register Machine Code: 0 Machine Cycle: 1 Operation: Page Register ← I Description: The immediate data I are loaded to the PR. Bit 3 is reserved. Bit ...
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Instruction Set Table 2, continued MOV PM0, #I Set/Reset Port Mode 0 register Machine Code: 0 Machine Cycle: 1 Operation: Set/Reset Port mode 0 register Description port is CMOS type port is ...
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Instruction Set Table 2, continued MOV PM3, #I Set/Reset Port Mode 3 register Machine Code: 0 Machine Cycle: 1 Operation: Set/Reset Port mode 3 register Description reserved The port RE is used as the output ...
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Instruction Set Table 2, continued MOV R, ACC Move ACC content to R Machine Code: 0 Machine Cycle: 1 Operation: R ← (ACC) Description: The contents of the ACC are loaded to the data memory location addressed ...
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Instruction Set Table 2, continued MOVA R, RC Input RC port data to ACC & R Machine Code: 0 Machine Cycle: 1 Operation: ACC , R ← [RC] Description: The input data on the input port RC are loaded into ...
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Instruction Set Table 2, continued MOV R, #I Load immediate data Machine Code: Machine Cycle: 1 Operation: R ← I Description: The immediate data I are loaded to the data memory location addressed R0. ...
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Instruction Set Table 2, continued MOV RD, R Output R content to RD port Machine Code: 1 Machine Cycle: 1 Operation: [RD] ← (R) Description: The contents of the data memory location addressed are output to ...
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Instruction Set Table 2, continued MOV TM0, #I Timer 0 set 0 Machine Code: Machine Cycle: 1 Operation: Timer 0 set The data specified loaded to the Timer 0 to start the timer. Description: MOV ...
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Instruction Set Table 2, continued MOV TM1L, R Move R content to TM1L 0 Machine Code: Machine Cycle: 1 Operation: TM1L ← (R) Description: The content of the data memory location addressed are loaded into the ...
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Instruction Set Table 2, continued MOV @R, WR Indirect load from Machine Code: 2 Machine Cycle: [PR (bit2, bit1, bit0) × 10H + (R)] ← WR Operation: Description: The contents of the WR are loaded to ...
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Instruction Set Table 2, continued MOVA R, HCFH Move HCF4~7 to ACC & Machine Code: Machine Cycle: 1 Operation: ACC, R ← HCF4~7 Description: The contents of HCF bit 4 to bit 7 (HCF4 to HCF7) are loaded ...
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Instruction Set Table 2, continued MOVA R, PAGE Move Page Register content to ACC & Machine Code: 1 Machine Cycle: ACC , R ← (Page Register) Operation: Description: The contents of the Page Register (PR) are loaded to ...
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Instruction Set Table 2, continued MOVA R, WR Move WR content to ACC & Machine Code: Machine Cycle: 1 Operation: ACC, R ← (WR) Description: The contents of the WR are loaded to the ACC and the data ...
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Instruction Set Table 2, continued MOVC R Move look-up table ROM addressed by TABL and TABH Machine code: 2 Machine Cycle: WR ← [(TABH) × 10H + (TABL)] Operation: Description: The contents of the look-up table ROM ...
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Instruction Set Table 2, continued ORLR R, ACC ACC 0 Machine Code: 1 Machine Cycle: ACC, R ← (R) ∧ (ACC) Operation: Description: The contents of the data memory location addressed and the ...
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Instruction Set Table 2, continued RRC R Rotate Right R with CF 0 Machine Code: 1 Machine Cycle: ACC.n, R.n ← (R.n+1); ACC.3, R.3 ← CF; CF ← R.0 Operation: Description: The contents of the ACC and the data memory ...
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Instruction Set Table 2, continued SBC WR, #I Subtract immediate data from WR with Borrow 0 Machine Code: 1 Machine Cycle: ACC ← (WR (CF) Operation: Description: The immediate data I and CF are binary subtracted from ...
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Instruction Set Table 2, continued SET CF Set CF Machine Code: 0 Machine Cycle: 1 Operation: Set CF Description: Set Carry Flag to 1. Flag Affected: CF SET PMF, #I Set ParaMeter Flag 0 Machine Code: 1 Machine Cycle: Set ...
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Instruction Set Table 2, continued SHRC R SHift Right R with CF and MSB = 0 Machine Code: 0 Machine Cycle: 1 Operation: ACC.n, R.n ← (R.n+1); ACC.3, R.3 ← ← R.0 Description: The contents of the ACC ...
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Instruction Set Table 2, continued SKB2 R If bit equal to 1 then skip Machine Code: 1 Machine Cycle: 1 Operation: PC ← (PC R.2 = 1“1” Description: If bit ...
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Instruction Set Table 2, continued SUB R, ACC Subtract ACC from R Machine Code: 0 Machine Cycle: 1 Operation: ACC ← (R) - (ACC) Description: The contents of the ACC are binary subtracted from the contents of the data memory ...
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Instruction Set Table 2, continued SUBR WR, #I Subtract immediate data from WR Machine Code: 0 Machine Cycle: 1 Operation: ACC, WR ← (WR Description: The immediate data I are binary subtracted from the contents of the WR ...
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Instruction Set Table 2, continued XRLR R, ACC Exclusive ACC Machine Code: 0 Machine Cycle: 1 Operation: ACC, R ← (R) EX (ACC) Description: The contents of the data memory location addressed and ...
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PACKAGE DIAMENSIONS 18-Lead PDIP (300 mil Preliminary W741E20X Base Plane Seating Plane Dimension in inch Dimension in mm Symbol Min. Nom. ...
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Package Dimensions, continued 20-Lead PDIP Preliminary W741E20X Base Plane Seating Plane Dimension in inch Dimension in mm Symbol Min. Nom. Max. ...
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Package Dimensions, continued 28-Lead PDIP Skinny Symbol Preliminary W741E20X Base Plane Dimension in Inches Dimension in mm Min. Nom. Max. Min. ...
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Package Dimensions, continued 20-Lead SOP (300mil SEATING PLANE Control demensions are in milmeters. Symbol θ Preliminary W741E20X ...
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Package Dimensions, continued 28-Lead SOP (300 mil SEATING PLANE Control demensions are in milmeters . Symbol Preliminary W741E20X Dimension in mm Dimension in Inches Min. Max. Min. Max. 0.093 0.104 2.35 A 2.65 0.10 ...
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Notes: Headquarters No. 4, Creation Rd. III, Science-Based Industrial Park, Hsinchu, Taiwan TEL: 886-3-5770066 FAX: 886-3-5792766 http://www.winbond.com.tw/ Voice & Fax-on-demand: 886-2-27197006 Taipei Office 11F, No. 115, Sec. 3, Min-Sheng East Rd., Taipei, Taiwan TEL: 886-2-27190505 FAX: 886-2-27197502 Note: All data ...