W78E516 Information Storage Devices, Inc, W78E516 Datasheet
W78E516
Available stocks
Related parts for W78E516
W78E516 Summary of contents
Page 1
... The W78E516B -bit microcontroller which has an in-system programmable FLASH-ROM for firmware updating. The instruction set of the W78E516B is fully compatible with the standard 8052. The W78E516B contains a 64K bytes of main FLASH-ROM and a 4K bytes of auxiliary FLASH-ROM which allows the contents of the 64KB main FLASH-ROM to be updated by the loader program located at the 4KB auxiliary FLASH-ROM ...
Page 2
... PIN CONFIGURATIONS 40-pin DIP (W78E516B) 1 VDD T2, P1.0 40 T2EX, P1 P0.0, AD0 P1 P0.1, AD1 4 P1.3 37 P0.2, AD2 P1 P0.3, AD3 6 P1.5 35 P0.4, AD4 7 34 P0.5, AD5 P1.6 8 P1.7 33 P0.6, AD6 9 32 P0.7, AD7 RST 10 RXD, P3 TXD, P3.1 11 ALE INT0, P3.2 PSEN 13 28 P2.7, A15 INT1, P3.3 T0, P3 P2.6, A14 T1, P3 P2.5, A13 WR, P3 P2.4, A12 ...
Page 3
... Another bit-addressable port P4 is also available and only 4 bits (P4<3:0>) can be used. This port address is located at 0D8H with the same function as that of port P1, Example: P4 REG 0D8H MOV P4, #0AH MOV A, P4 SETB P4.0 CLR P4.1 DESCRIPTIONS ; Output data "A" through P4.0 P4.3. ; Read P4 status to Accumulator. ; Set bit P4.0 ; Clear bit P4 W78E516B Publication Release Date: February 2000 Revision A3 ...
Page 4
... RAM The internal data RAM in the W78E516B is 512 bytes divided into two banks: 256 bytes of scratchpad RAM and 256 bytes of AUX-RAM. These RAMs are addressed by different ways. RAM 0H 127H can be addressed directly and indirectly as the same as in 8051. Address pointers are R0 and R1 of the selected register bank ...
Page 5
... Timers 0 and 1. Clock The W78E516B is designed with either a crystal oscillator or an external clock. Internally, the clock is divided by two before it is used by default. This makes the W78E516B relatively insensitive to duty cycle variations in the clock. Crystal Oscillator The W78E516B incorporates a built-in crystal oscillator. To make the oscillator work, a crystal must be connected across pins XTAL1 and XTAL2 ...
Page 6
... An internal trigger circuit in the reset line is used to deglitch the reset line when the W78E516B is used with an external RC network. The reset logic also has a special glitch removal circuit that ignores glitches on the reset line. During reset, the ports are initialized to FFH, the stack pointer to 07H, PCON (with the exception of bit 4) to 00H, and all of the other SFR registers except SBUF to 00H ...
Page 7
... APROM) and one 4K byte of auxiliary FLASH-ROM bank for loader program (called LDROM). In the normal operation, the microcontroller executes the code in the APROM. If the content of APROM needs to be modified, the W78E516B allows user to activate the In-System Programming (ISP) mode by setting the CHPCON register. The CHPCON is read-only by default, software must write two specific values 87H, then 59H sequentially to the CHPENR register to enable the CHPCON write attribute ...
Page 8
... Enable on-chip AUX-RAM. 0: Disable the on-chip AUX-RAM FUNCTION CTRL<3:0> OEN 0 0010 1 0 0001 1 0 0000 0 1 0010 1 1 0001 1 1 0000 0 FUNCTION - 8 - W78E516B CEN SFRAH, SFRAL SFRFD Address in Data in 0 Address in Data out Address in Data in 0 Address in Data out X X ...
Page 9
... Must set FBOOTSL The Program Location Select. 0: The Loader Program locates at the 64 KB APROM. 4KB LDROM is destination for re-programming. 1: The Loader Program locates at the 4 KB memory bank. 64KB APROM is destination for re-programming. Publication Release Date: February 2000 - 9 - W78E516B Revision A3 ...
Page 10
... W78E516B to enter the F04KBOOT mode. After power on of personal computer, you can release both buttons and finish the in-system programming procedure to update the APROM code. In application system design, user must take care of the P2, P3, ALE, EA and PSEN pin value at reset to prevent from accidentally activating the programming mode or F04KBOOT mode ...
Page 11
... In-System Programming mode) CPU will be wakened by interrupt and re-boot from 4KB LDROM to execute the loader program. Go Part 1:64KB APROM procedure of entering In-System Programming Mode Execute the normal application program END Publication Release Date: February 2000 - 11 - W78E516B Revision A3 ...
Page 12
... MOV CHPCON,#83H Setting control registers for programming: MOV SFRAH,#ADDRESS_H MOV SFRAL,#ADDRESS_L MOV SFRFD,#DATA MOV SFRCN,#21H Executing new code from address 00H in the 64KB APROM W78E516B Yes No Hardware Reset to re-boot from new 64 KB APROM. (S/W reset is invalid in F04KBOOT Mode) END ...
Page 13
... Reserved bits must be kept in logic 1. Lock bit This bit is used to protect the customer's program code in the W78E516B. It may be set after the programmer finishes the programming and verifies sequence. Once this bit is set to logic 0, both the FLASH ROM data and Special Setting Registers can not be accessed again. ...
Page 14
... W78E516B ...
Page 15
... Oscillator Control W78E516B/E516 allow user to diminish the gain of on-chip oscillator amplifier by using programmer to set the bit B7 of security register. Once B7 is set half of gain will be decreased. Care must be taken if user attempts to diminish the gain of oscillator amplifier, reducing a half of gain may improperly affect the external crystal operation at high frequency above 24 MHz ...
Page 16
... V +0.2 IH2 DD V 3.5 V +0.2 IH3 0.45 OL1 V - 0.45 OL2 Isk1 4 12 Isk2 2.4 - OH1 V 2.4 - OH2 Isr1 -120 -250 Isr2 -8 -20 approximates to 2V W78E516B TEST CONDITIONS UNIT 0.45V ...
Page 17
... T - AAS AAH APL PDA T 0 PDH T 0 PDZ ALW PSW CP Publication Release Date: February 2000 - 17 - W78E516B MAX. UNIT NOTES - 40 MHz - - MAX. UNIT NOTES - - ...
Page 18
... DAD DWD DWR CP CP SYMBOL MIN. TYP TCP - PDS PDH T 1 TCP - PDA - 18 - W78E516B MAX. UNIT NOTES CP MAX. UNIT MAX. ...
Page 19
... XTAL1 ALE PSEN PORT 2 A0-A7 PORT ALW T APL T PSW T AAS T PDA T T PDH, PDZ A0-A7 A0-A7 Code Data A8-A15 DATA T DAR T DDA T DDH, T DRD - 19 - W78E516B A0-A7 Data A0- DDZ Publication Release Date: February 2000 Revision A3 ...
Page 20
... Timing Waveforms, continued Data Write Cycle S4 S5 XTAL1 ALE PSEN PORT 2 PORT 0 A0-A7 WR Port Access Cycle XTAL1 ALE T PDS PORT INPUT SAMPLE A8-A15 DATA OUT T DAD T T DWR DAW PDH - 20 - W78E516B DWD S1 T PDA DATA OUT ...
Page 21
... A12 T 0 P2.4 26 A13 T 1 P2.5 27 A14 P2.6 P1.0 28 A15 P2.7 P1 P1.3 WR P1.4 29 PSEN P1.5 30 ALE P1.6 11 TXD P1.7 10 RXD Figure A C1 47P 30P 15P 10P W78E516B ...
Page 22
... INT0 P2.2 23 A10 P2.3 24 A11 INT1 P2.4 25 A12 P2.5 26 A13 P2.6 27 A14 P2.7 28 P1 P1.3 29 P1.4 PSEN 30 P1.5 ALE 11 P1.6 TXD 10 P1.7 RXD Figure W78E516B ...
Page 23
... E Base Plane A 1 Seating Plane W78E516B Dimension in inch Dimension in mm Symbol Min. Nom. Max. Min. Nom. 0.210 A 0.010 0.254 A 1 0.155 0.160 0.150 3.81 3.937 A 2 0.016 0.018 0.022 0.406 0.457 B 0.048 ...
Page 24
... Application Note: In-system Programming Software Examples This application note illustrates the in-system programmability of the Winbond W78E516B FLASH-ROM microcontroller. In this example, microcontroller will boot from 64 KB APROM bank and waiting for a key to enter in-system programming mode for re-programming the contents APROM. While entering in-system programming mode, microcontroller executes the loader program in 4KB LDROM bank ...
Page 25
... MOV TCON,#00H ; TIMER0 STOP MOV IP,#00H ; IP = 00H MOV IE,#82H ; TIMER0 INTERRUPT ENABLE FOR WAKE-UP FROM IDLE MODE MOV R6,#FEH ; TL0 = FEH Publication Release Date: February 2000 - 25 - W78E516B Revision A3 ...
Page 26
... C4H SFRAH EQU C5H SFRFD EQU C6H SFRCN EQU C7H ORG 000H LJMP 100H ; JUMP TO MAIN PROGRAM ;************************************************************************ ;* 1. TIMER0 SERVICE VECTOR ORG = 0BH ;************************************************************************ ORG 000BH CLR TR0 ; TR0 = 0, STOP TIMER0 MOV TL0,R6 MOV TH0,R7 RETI ;************************************************************************ ;* 4KB LDROM MAIN PROGRAM ;************************************************************************ ORG 100H - 26 - W78E516B ...
Page 27
... Publication Release Date: February 2000 - 27 - W78E516B Revision A3 ...
Page 28
... ENTER IDLE MODE (FOR ERASE OPERATION) ;********************************************************************* ;* BLANK CHECK ;********************************************************************* MOV SFRCN,#0H ; READ 64KB APROM MODE MOV SFRAH,#0H ; START ADDRESS = 0H MOV SFRAL,#0H MOV R6,#FBH ; SET TIMER FOR READ OPERATION, ABOUT 1.5 S. MOV R7,#FFH MOV TL0,R6 MOV TH0,R7 BLANK_CHECK_LOOP: SETB TR0 ; ENABLE TIMER W78E516B ...
Page 29
... MOV PCON,#01H ; ENTER IDLE MODE (PRORGAMMING) INC DPTR INC R2 CJNE R2,#0H,PROG_D_64K INC R1 MOV SFRAH,R1 CJNE R1,#0H,PROG_D_64K ;***************************************************************************** ; * VERIFY 64KB APROM BANK ;***************************************************************************** MOV R4,#03H ; ERROR COUNTER MOV R6,#FBH ; SET TIMER FOR READ VERIFY, ABOUT 1.5 S. MOV R7,#FFH Publication Release Date: February 2000 - 29 - W78E516B Revision A3 ...
Page 30
... MOV TL0,R6 MOV TH0,R7 MOV DPTR,#0H ; The start address of sample code MOV R2,#0H ; Target low byte address MOV R1,#0H ; Target high byte address MOV SFRAH,R1 ; SFRAH, Target high address MOV SFRCN,#00H ; SFRCN = 00 (Read ROM CODE W78E516B ...
Page 31
... PROGRAMMING COMPLETLY, SOFTWARE RESET CPU ;****************************************************************************** MOV CHPENR,#87H ; CHPENR = 87H MOV CHPENR,#59H ; CHPENR = 59H MOV CHPCON,#83H ; CHPCON = 83H, SOFTWARE RESET. ERROR_64K: DJNZ R4,UPDATE_64K ; IF ERROR OCCURS, REPEAT 3 TIMES IN-SYSTEM PROGRAMMING FAIL, USER'S PROCESS TO DEAL WITH IT Publication Release Date: February 2000 - 31 - W78E516B Revision A3 ...
Page 32
... TEL: 886-2-27190505 FAX: 886-2-27197502 Note: All data and specifications are subject to change without notice. Winbond Electronics North America Corp. Winbond Memory Lab. Winbond Microelectronics Corp. Winbond Systems Lab. 2727 N. First Street, San Jose, CA 95134, U.S.A. TEL: 408-9436666 FAX: 408-5441798 - 32 - W78E516B ...