W83697HFFDC Information Storage Devices, Inc, W83697HFFDC Datasheet
W83697HFFDC
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W83697HFFDC Summary of contents
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W83697HF/F WINBOND I/O ...
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W83697HF/F Data Sheet Revision History Pages Dates 1 n.a. 08/23/99 2 98, 107, 116 11/15/99 3 All 11/15/2000 All 4 9/3/2001 2/19/2002 Please note that all data and specifications are subject to change without ...
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GENERAL DESCRIPTION .....................................................................................................1 1. PIN DESCRIPTION .....................................................................................................5 1.1 LPC INTERFACE................................................................................................................................................................ 6 1.2 FDC INTERFACE................................................................................................................................................................ 7 1.3 MULTI-MODE PARALLEL PORT...................................................................................................................................8 1.4 SERIAL PORT INTERFACE............................................................................................................................................ 13 1.5 INFRARED PORT............................................................................................................................................................. 14 1.6 FRESH ROM INTERFACE .............................................................................................................................................. 14 1.7 HARDWARE MONITOR INTERFACE ........................................................................................................................ 15 ...
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Data Rate Register (DR Register) (Write base address + 4)...........................................................................40 3.2.7 FIFO Register (R/W base address + 5)................................................................................................................41 3.2.8 Digital Input Register (DI Register) (Read base address + 7)....................................................................... 44 3.2.9 Configuration Control Register (CC Register) (Write base address ...
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ENHANCED PARALLEL PORT (EPP).......................................................................................................................... 64 6.2.1 Data Swapper...........................................................................................................................................................65 6.2.2 Printer Status Buffer................................................................................................................................................65 6.2.3 Printer Control Latch and Printer Control Swapper .......................................................................................66 6.2.4 EPP Address Port.....................................................................................................................................................66 6.2.5 EPP Data Port 0-3...................................................................................................................................................67 6.2.6 Bit Map of Parallel Port and EPP Registers......................................................................................................67 ...
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LPC interface............................................................................................................................................................ 82 9.3 ANALOG INPUTS ............................................................................................................................................................ 84 9.3.1 Monitor over 4.096V voltage:...............................................................................................................................84 9.3.2 Monitor negative voltage:.....................................................................................................................................85 9.3.3 Temperature Measurement Machine....................................................................................................................86 9.4 FAN SPEED COUNT AND FAN SPEED CONTROL.................................................................................................. 87 9.4.1 Fan speed count .......................................................................................................................................................87 9.4.2 Fan speed control....................................................................................................................................................89 ...
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BEEP Control Register 2-- Index 57h (Bank 0)........................................................................................... 106 9.7.21 Chip ID -- Index 58h (Bank 0)......................................................................................................................... 107 9.7.22 Reserved Register -- Index 59h (Bank 0) ......................................................................................................107 9.7.23 PWMOUT1 Control -- Index 5Ah (Bank 0).................................................................................................... 108 9.7.24 PWMOUT2 Control ...
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CPUT1 Target Temperature Register/ Fan 1 Target Speed Register -- Index 05h................................. 120 9.7.56 CPUT2 Target Temperature Register/ Fan 2 Target Speed Register -- Index 06h................................. 120 9.7.57 Tolerance of Target Temperature or Target Speed Register -- Index 07h ...
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ORDERING INSTRUCTION...................................................................................149 12. HOW TO READ THE TOP MARKING..................................................................149 13. PACKAGE DIMENSIONS.......................................................................................150 W83697HF/F Publication Release Date: Feb. 2002 - VII - Revision 0.70 ...
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GENERAL DESCRIPTION The W83697HF is evolving product from Winbond's most popular I/O family. They feature a whole new interface, namely LPC (Low Pin Count) interface, which will be supported in the new generation chip-set. This interface as its name suggests ...
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The W83697HF provides Flash ROM interface. That can support legacy flash ROM. The W83697HF support hardware status monitoring for personal computers. It can be used to monitor several critical hardware parameters of the system, including power supply ...
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UART Two high-speed 16550 compatible UARTs with 16-byte send/receive FIFOs MIDI compatible Fully programmable serial-interface characteristics: --- 8-bit characters --- Even, odd or no parity bit generation/detection --- 1, 1 stop bits generation Internal ...
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Flash ROM Interface Support flash ROM General Purpose I/O Ports 48 programmable general purpose I/O ports General purpose I/O ports can serve as simple I/O ports, watch dog timer output, power LED output, infrared I/O pins, suspend ...
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PIN CONFIGURATION FOR 697HF 103 VTIN2 104 VTIN1 105 AVCC 106 VREF 107 VCORE 108 +3.3VIN 109 +12VIN 110 -12VIN 111 -5VIN AGND 112 FANIO2 113 FANIO1 114 FANPWM2 ...
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PIN DESCRIPTION Note: Please refer to Section 13.2 DC CHARACTERISTICS for details. I TTL level bi-directional pin with 8 mA source-sink capability I/O 12t - TTL level bi-directional pin with 12 mA source-sink capability I/O 12tp3 - ...
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FDC Interface SYMBOL PIN I/O DRVDEN0 INDEX MOA DSB DSA MOB DIR STEP WD# 10 ...
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FDC Interface, continued SYMBOL PIN I/O HEAD DSKCHG 1.3 Multi-Mode Parallel Port The following pins have alternate functions, which are controlled by CR28 and L3-CRF0. SYMBOL PIN I/O SLCT ...
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Multi-Mode Parallel Port, continued SYMBOL PIN I/O BUSY ACK ERR FUNCTION PRINTER MODE: An active high input indicates ...
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Multi-Mode Parallel Port, continued SYMBOL PIN I/O SLIN INIT AFD FUNCTION PRINTER MODE: SLIN# Output line for detection ...
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Multi-Mode Parallel Port, continued SYMBOL PIN I/O STB PD0 42 I/O 12t PD1 41 I/O 12t PD2 40 I/O 12t FUNCTION PRINTER ...
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Multi-Mode Parallel Port, continued SYMBOL PIN I/O PD3 39 I/O 12t PD4 38 I/O 12t PD5 37 I/O 12t - - PD6 36 I/OD 12t - OD 12 PD7 35 I/OD ...
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Serial Port Interface SYMBOL PIN I/O CTSA CTSB# 55 DSRA DSRB I/O 8t RTSA# HEFRAS 57 I/O 8t RTSB# 50 I/O 8t DTRA# PNPCSV# 58 I/O 8t DTRB# SINA 51 IN ...
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Infrared Port SYMBOL PIN I/O IRRX IRTX 65 OUT 12t CIRRX# 100 IN t 1.6 Fresh ROM Interface SYMBOL PIN I/O XA18-XA16 66-68 I/O 12t GP57-GP55 I/OD 12t XA15-XA10 69-74 I/O 12t GP47-GP42 I/OD 12t XA9-XA8 ...
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Hardware Monitor Interface SYMBOL PIN I/O CASEOPEN# 101 IN t VBAT 102 Power VTIN2 103 AIN VTIN1 104 AIN VREF 106 AOUT VCORE 107 AIN +3.3VIN 108 AIN +12VIN 109 AIN -12VIN 110 AIN -5VIN 111 AIN FANIO[2:1] 113- ...
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Game Port & MIDI Port SYMBOL PIN I/O MSI 119 INt GP51 I/OD 12 WDTO OD 24t MSO 120 OUT 12t GP50 I/OD 12 PLED OD 24t GPAS2 121 INcs GP17 I/OD 12 GPBS2 122 INcs GP16 I/OD 12 ...
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POWER PINS SYMBOL PIN VCC 5, 45, 75, VSB 99 VCC3V 22 AVCC 105 AGND 112 GND 18, 60, 90, FUNCTION +5V power supply for the digital circuitry. +5V stand -by power supply for the digital circuitry. +3.3V power ...
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LPC (LOW PIN COUNT) INTERFACE LPC interface is to replace ISA interface serving as a bus interface between host (chip-set) and peripheral (Winbond I/O). Data transfer on the LPC bus are serialized over a 4 bit bus. The general ...
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FDC FUNCTIONAL DESCRIPTION 3.1 W83697HF FDC The floppy disk controller of the W83697HF integrates all of the logic required for floppy disk control. The FDC implements a PC/AT or PS/2 solution. values. The FIFO provides better system performance in ...
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At the start of a command the FIFO is always disabled and command parameters must be sent based upon the RQM and DIO bit settings in the main status register. When the FDC enters the command execution phase, it clears ...
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Perpendicular Recording Mode The FDC is also capable of interfacing directly to perpendicular recording floppy drives. Perpendicular recording differs from the traditional longitudinal method in that the magnetic bits are oriented vertically. This scheme packs more data bits into ...
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EOT: End of track FIFOTHR: FIFO Threshold GAP: Gap length selection GPL: Gap Length H: Head number HDS: Head number select HLT: Head Load Time HUT: Head Unload Time LOCK: Lock EFIFO, FIFOTHR, PTRTRK bits prevent affected by software reset ...
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Read Data PHASE R Command W MT MFM Execution Result ...
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Read Deleted Data PHASE R Command W MT MFM Execution Result ...
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Read A Track PHASE R Command W 0 MFM Execution Result ...
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Read ID PHASE R Command W 0 MFM Execution Result HDS -------------------- ST0 ----------------------- -------------------- ST1 ...
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Verify PHASE R Command W MT MFM Execution Result HDS ...
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Version PHASE R Command Result (7) Write Data PHASE R Command W MT MFM Execution Result ...
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Write Deleted Data PHASE R Command W MT MFM Execution Result ...
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Format A Track PHASE R Command W 0 MFM Execution W for Each W Sector W Repeat: W Result (10) Recalibrate PHASE R/W ...
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Sense Interrupt Status PHASE R Command Result R R (12) Specify PHASE R Command ---------SRT ----------- | --------- HUT ---------- | W |------------ HLT ----------------------------------| ND (13) ...
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Relative Seek PHASE R Command W 1 DIR -------------------- RCN ---------------------------- | (16) Dumpreg PHASE R Command Result R ----------------------- PCN-Drive 0-------------------- R ----------------------- PCN-Drive 1 ------------------- ...
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Sense Drive Status PHASE R Command Result R (20) Invalid PHASE R Command W Result HDS ---------------- ...
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Register Descriptions There are several status, data, and control registers in W83697HF. These registers are defined below: ADDRESS OFFSET base address + 0 base address + 1 base address + 2 base address + 3 base address + 4 ...
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HEAD (Bit 3): This bit indicates the complement of HEAD# output. 0 side 0 1 side 1 INDEX# (Bit 2): This bit indicates the value of INDEX# WP# (Bit 1): 0 disk is write-protected 1 disk is not write-protected DIR ...
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HEAD# (Bit 3): This bit indicates the value of HEAD# 0 side 1 1 side 0 INDEX (Bit 2): This bit indicates the complement of INDEX# output. WP (Bit 1): 0 disk is not write-protected 1 disk is write-protected DIR# ...
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MOT EN B (Bit 1) This bit indicates the complement of the MOB# output pin. MOT EN A (Bit 0) This bit indicates the compleme nt of the MOA# output pin. In PS/2 Model 30 mode, the bit definitions for ...
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Digital Output Register (DO Register) (Write base address + 2) The Digital Output Register is a write-only register controlling drive motors, drive selection, DRQ/IRQ enable, and FDC resetting. All the bits in this register are cleared by the MR ...
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Media ID1 Media ID0 (Bit 7, 6): These two bits are read only. These two bits reflect the value of CR8 bit 3, 2. Drive type ID1 Drive type ID0 (Bit 5, 4): These two bits reflect two of the ...
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Data Rate Register (DR Register) (Write base address + 4) The Data Rate Register is used to set the transfer rate and write precompensation. The data rate of the FDC is programmed by the CC REGISTER for PC-AT and ...
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DATA RATE 250 KB/S 300 KB/S 500 KB/S 1 MB/S 2 MB/S DRATE1 DRATE0 (Bit 1, 0): These two bits select the data rate of the FDC and reduced write current control. 500 KB/S (MFM), 250 KB/S (FM), RWC = ...
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Status Register 0 (ST0) 7 1-0 4 Status Register 1 (ST1 US1, US0 Drive Select: 00 Drive A selected 01 Drive B selected 10 Drive C selected 11 Drive D ...
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Status Register 2 (ST2 Status Register 3 (ST3 (Missing Address Mark in Data Field the FDC cannot find a data address mark (or the address mark has been ...
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Digital Input Register (DI Register) (Read base address + 7) The Digital Input Register is an 8-bit read-only register used for diagnostic purposes PC/ only Bit 7 is checked by the BIOS. When the register ...
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DSKCHG (Bit 7): This bit indicates the status of DSKCHG# input. Bit 6 -4: These bits are always a logic 1 during a read. DMAEN (Bit 3): This bit indicates the value of DO REGISTER bit 3. NOPREC (Bit 2): ...
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UART PORT 4.1 Universal Asynchronous Receiver/Transmitter (UART A, UART B) The UARTs are used to convert parallel data into serial format on the transmit side and convert serial data to pa rallel format on the receiver side. The serial ...
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TABLE 4-1 UART Register Bit Map Register Address Base + 0 Receiver RBR RX Data Buffer BDLAB = 0 Register (Read Only Transmitter TBR TX Data Buffer Register BDLAB = 0 (Write Only Interrupt Control ICR ...
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Bit 4: EPE. This bit describes the number of logic 1's in the data word bits and parity bit only when bit 3 is programmed. When this bit is set, an even number of logic 1's are sent or checked. ...
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Bit 7: RFEI. In 16450 mode, this bit is always set to a logic 0. In 16550 mode, this bit is set to a logic 1 when there is at least one parity bit error, no stop bit error or ...
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Handshake Control Register (HCR) (Read/Write) This register controls the pins of the UART used for handshaking peripherals such as modem, and controls the diagnostic mode of the UART Bit 4: When this bit is set ...
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Handshake Status Register (HSR) (Read/Write) This register reflects the current state of four input pins for handshake peripherals such as a modem and records changes on these pins Bit 7: This bit is the opposite of the ...
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UART FIFO Control Register (UFR) (Write only) This register is used to control the FIFO functions of the UART Bit 6, 7: These two bits are used to set the active level for the receiver FIFO ...
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Interrupt Status Register (ISR) (Read only) This register reflects the UART interrupt status, which is encoded by different interrupt sources into 3 bits Bit 7, 6: These two bits are set to a logical 1 when UFR ...
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Interrupt Control Register (ICR) (Read/Write) This 8 -bit register allows the five types of controller interrupts to activate the interrupt output signal separately. The interrupt system can be totally disabled by resetting bits 0 through 3 of the Interrupt ...
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User-defi ned Register (UDR) (Read/Write) This is a temporary register that can be accessed and defined by the user. TABLE 4-5 BAUD RATE TABLE BAUD RATE FROM DIFFERENT PRE-DIVIDER Pre-Div: 13 Pre-Div:1.625 1.8461M Hz 14.769M Hz 50 400 75 ...
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CIR RECEIVER PORT 5.1 CIR Registers 5.1.1 Bank0.Reg0 - Receiver Buffer Registers (RBR) (Read) Receiver Buffer Register is read only. When the CIR pulse train has been detected and passed by the internal signal filter, the data samped and ...
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Bank0~3.Reg3 - CIR Control Register 0/Bank Select Register (CTR0/BSR) (BANK0~3) Power on default <7:0> = 00000000 binary Bit Name Read/Write 7-6 BNK_SEL<1:0> Read/Write 5-4 RXFTL1/0 Read/Write 3 TMR_TST Read/Write 2 EN_TMR Read/Write 1 RXF_RST Read/Write 0 TMR_CLK Read/Write Description ...
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Bank0.Reg4 - CIR Control Register (CTR) Power on default <7:0> = 0010,1001 binary Bit Name Read/Write 7-5 RX_FR<2:0> Read/Write 4-0 RX_FSL<4:0> Read/Write Table: Low Frequency range select of receiver. 001 RX_FSL4~0 Min. 00010 26.1 00011 28.2 00100 29.4 00101 ...
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Bank0.Reg5 - UART Line Status Register (USR) Power on default <7:0> = 0000,0000 binary Bit Name Read/Write 7-3 Reserved - 2 RX_TO Read/Write 1 OV_ERR Read/Write 0 RDR Read/Write 5.1.7 Bank0.Reg6 - Remote Infrared Config Register (RIR_CFG) Power on ...
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Bank0.Reg6 - Remote Infrared Config Register (RIR_CFG), continued Power on default <7:0> = 0000,0000 binary Bit Name Read/Write 5-4 LP_SL<1:0> Read/Write 3-2 RXDMSL<1:0> Read/Write 1 PRE_DIV Read/Write 0 RXINV Read/Write 5.1.8 Bank0.Reg7 - User Defined Register (UDR/AUDR) Power on ...
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Bank1.Reg0~1 - Baud Rate Divisor Latch (BLL/BHL) The two registers of BLL and BHL are baud rate divisor latch in the legacy UART/SIR/ASK-IR mode. Read/Write these registers, if set in Advanced UART mode, will occur backward operation, that is, ...
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Bank1.Reg2 - Version ID Regiister I (VID) Power on default <7:0> = 0001,0000 binary Bit Name Read/Write 7-0 VID Read Only 5.1.11 Bank0~3.Reg3 - CIR Control Register 0/Bank Select Register (CTR0/BSR) (BANK0~3) This register is defined same as in ...
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PARALLEL PORT 6.1 Printer Interface Logic The parallel port of the W83627HF makes possible the attachment of variou s devices that accept eight bits of parallel data at standard TTL level. The W83627HF supports an IBM XT/AT compatible parallel ...
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TABLE 6-1-2 PARALLEL PORT CONNECTOR AND PIN DEFINITIONS HOST PIN NUMBER OF CONNECTOR W83627HF ...
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Data Swapper The system microprocessor can read the contents of the printer's data latch by reading the data swapper. 6.2.2 Printer Status Buffer The system microprocessor can read the printer status by reading the address of the printer status ...
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Printer Control Latch and Printer Control Swapper The system microprocessor can read the contents of the printer control latch by reading the printer control swapper. Bit definitions are as follows: 1 Bit 7, 6: These two bits are a ...
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The contents of DB0-DB7 are buffered (non-inverting) and output to ports PD0-PD7 during a write operation. The leading edge of IOW# trailing edge of IOW# latches the data for the duration of the EPP write cycle. PD0-PD7 ports are read ...
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EPP Pin Descriptions EPP NAME TYPE nWrite O Denotes an address or data read or write operation. PD<0:7> I/O Bi-directional EPP address and data bus. Intr I Used by peripheral device to interrupt the host. nWait I Inactive to ...
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Extended Capabilities Parallel (ECP) Port This port is software and hardware compatible with existing parallel ports may be used as a standard printer mode if ECP is not required. It provides an automatic high burst-bandwidth channel that ...
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Publication Release Date: Feb. 2002 - 70 - W83697HF/F Revision 0.70 ...
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Data and ecpAFifo Port Modes 000 (SPP) and 001 (PS/2) (Data Port) During a write operation, the Data Register latches the contents of the data bus on the rising edge of the input. The contents of this register are ...
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Bit 7: This bit reflects the complement of the Busy input. Bit 6: This bit reflects the nAck input. Bit 5: This bit reflects the PError input. Bit 4: This bit reflects the Select input. Bit 3: This bit reflects ...
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Port Data FIFO) Mode = 010 This mode is defined only for the forward direction. The standard parallel port protocol is used by a hardware handshake to the peripheral to transmit bytes written or DMAed from the ...
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Bit 5-3: Reflect the IRQ resource assigned for ECP port. cnfgB[5:3] 000 reflect other IRQ resources selected by PnP register (default) 001 IRQ7 010 IRQ9 011 IRQ10 100 IRQ11 101 IRQ14 110 IRQ15 111 IRQ5 Bit 2-0: These five bits ...
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Bit 4: Read/Write (Valid only in ECP Mode) 1 Disables the interrupt generated on the asserting edge of nFault. 0 Enables an interrupt pulse on the high to low edge of nFault. If nFault is asserted (interrupt) an interrupt will ...
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ECP Pin Descriptions NAME TYPE nStrobe (HostClk) PD<7:0> I/O nAck (PeriphClk) Busy (PeriphAck) PError (nAckReverse) Select (Xflag) nAut oFd (HostAck) nFault (nPeriphRequest) nInit (nReverseRequest) nSelectIn (ECPMode) DESCRIPTION O The nStrobe registers data or address into the slave on the ...
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ECP Operation The host must negotiate on the parallel port to determine if the peripheral supports the ECP protocol before ECP operation. After negotiation necessary to initialize some of the port bits. The following are required: (a) ...
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DMA Transfers DMA transfers are always to or from the ecpDFifo, tFifo, or CFifo. The DMA uses the standard PC DMA services. The ECP requests DMA transfers from the host by activating the PDRQ pin. The DMA will empty ...
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GENERAL PURPOSE I/O W83697HF provides 24 input/output ports that can be individually configured to perform a simple basic I/O function or a pre-defined alternate function. Those 24 GP I/O ports are divided into three groups, each group contains 8 ...
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Table 7.2 GP I/O PORT DATA REGISTER GP1 GP2 GP3 REGISTER BIT GP I/O PORT ASSIGNMENT BIT 0 GP10 BIT 1 GP11 BIT 2 GP12 BIT 3 GP13 BIT 4 GP14 BIT 5 GP15 BIT 6 GP16 BIT 7 GP17 ...
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Figure 7.1 Publication Release Date: Feb. 2002 - 81 - W83697HF/F Revision 0.70 ...
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ACPI REGISTERS FEATURES W83697HF supports both ACPI and legacy power managements. management block generates an SMI interrupt in the legacy mode and an PME interrupt in the ACPI mode. The new ACPI feature routes SMI / PME SMI / ...
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HARDWARE MONITOR 9.1 General Description The W83697HF can be used to monitor several critical hardware parameters of the system, including power supply voltages, fan speeds, and temperatures, which are very important for a high-end computer system to work stable ...
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ISA ISA Data Address Bus Bus Index Register Data Register Figure 9.1 : ISA interface access diagram W83697HF/F Configuration Register 40h SMI# Status/Mask Registers 41h, 42h, 44h, 45h ...
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Analog Inputs The maximum input voltage of the analog pin is 4.096V because the 8-bit ADC has a 16mv LSB. Really, the application of the PC monitoring would most often be connected to power suppliers. The CPU V-core voltage ...
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The Pin 61 is connected to 5VSB voltage. W83697HF monitors this voltage and the internal two serial resistors are 17K and 33K maximum input voltage. 9.3.2 Monitor negative voltage: The negative voltage should be connected two series resistors and a ...
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Temperature Measurement Machine The temperature data format is 8-bit two's-complement for sensor 1 and 9-bit two's-complement for sensor 2. The 8-bit temperature data can be obtained by reading the CR[27h]. The 9-bit temperature data can be obtained by reading ...
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Bipolar Transistor Temperature Sensor B OR Pentium II CPU Therminal Diode 9.4 FAN Speed Count and FAN Speed Control 9.4.1 Fan speed count Inputs are provides for signals from fans equipped with tachometer outputs. The level of these signals should ...
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Divisor Nominal PRM 1 8800 2 (default) 4400 4 2200 8 1100 16 550 32 275 64 137 128 68 +12V +5V Pull-up resister 4.7K Ohms diode +12V Fan Input FAN Out GND FAN Connector Fan with Tach Pull-Up to ...
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Fan speed control The W83697HF provides 2 sets for fan PWM speed control. The duty cycle of PWM can be programmed by a 8-bit registers which are defined in the Bank0 CR5A and CR5B. The default duty cycle is ...
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SMI# interrupt mode 9.5.1 Voltage SMI# mode : SMI# interrupt for voltage is Two-Times Interrupt Mode. Voltage exceeding high limit or going below low limit will causes an interrupt if the previous interrupt has been reset by reading all ...
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The W83697HF temperature sensor 1 SMI# interrupt has two modes: (1) Comparator Interrupt Mode Setting the T (Temperature Hysteresis) limit to 127 ° C will set temperature sensor 1 SMI# to the HYST Comparator Interrupt Mode. Temperature exceeds ...
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The W83697HF temperature sensor 2 SMI# interrupt has two modes and it is programmed at CR[4Ch] bit 6. (1) Comparator Interrupt Mode: Temperature exceeding T O Interrupt Status Register. Once an interrupt event has occurred by exceeding T temperature ...
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OVT# interrupt mode The OVT# signal is only related with temperature sensor 2. 9.6.1 The W83697HF temperature sensor 2 Over-Temperature (OVT#) has the following modes (1) Comparator Mode(Default): Setting Bank1/2 CR[52h] bit will set OVT# signal ...
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To T HYST OVT# (Comparator Mode; default) OVT# (Interrupt Mode) *Interrupt Reset when Temperature 2/3 is read OVT# pin signal in ACPI mode ('C) 100 OVT# W83697HF ...
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REGISTERS AND RAM 9.7.1 Address Register (Port x5h) Data Port: Power on Default Value Attribute: Size: Bit7: Read Only The logical 1 indicates the device is busy because of a Serial Bus transaction or another LPC bus transaction. With ...
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Address Pointer Index (A6-A0) Registers and RAM A6-A0 in Configuration Register Interrupt Status Register 1 Interrupt Status Register 2 SMI#Ý Mask Register 1 SMIÝ Mask Register 2 NMI Mask Register 1 NMI Mask Register 2 Fan Divisor Register Reserved Device ...
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Address Pointer Index (A6-A0), continued Registers and RAM A6-A0 in POST RAM Value RAM Value RAM Temperature 2 Registers 50h-56h Reserved 50h-56h Additional Configuration Registers 50h-5Dh Power On Value of Hex Registers: <k7:0>in Binary 00-1Fh 20-3Fh 60-7Fh Bank1 Bank2 Bank4 ...
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Data Register (Port x6h) Data Port: Power on Default Value Attribute: Size: Bit 7-0: Data to be read from written to RAM and Register. 9.7.3 Configuration Register Register Location: Power on Default Value Attribute: Size: 7 ...
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W83697HF/F Publication Release Date: Feb. 2002 - 100 - Revision 0.70 ...
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Interrupt Status Register 1 Register Location: Power on Default Value Attribute: Size: Bit 7: A one indicates the fan count limit of FAN2 has been exceeded. Bit 6: A one indicates the fan count limit of FAN1 has been ...
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Bit 7-6:Reserved.This bit should be set to 0. Bit 5: Reserved. Bit 4: A one indicates case has been opened. Bit 3: Reserved. Bit 2: A one indicates a High or Low limit of -5VIN has been exceeded. Bit1: A ...
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W83697HF/F Publication Release Date: Feb. 2002 - 103 - Revision 0.70 ...
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Reserved Register 9.7.9 Chassis Clear Register -- Index 46h Register Location: Power on Default Value Attribute: Size: 7 Bit 7: Set 1 , clear case open event. This bit self clears after clearing case open event. Bit 6-0:Reserved. This ...
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Value RAM Index 20h- 3Fh or 60h - 7Fh (auto-increment) Address A6-A0 Address A6-A0 with Auto-Increment 20h 60h 21h 61h 22h 62h 23h 63h 24h 64h 25h 65h 26h 66h 27h 67h 28h 68h 29h 69h 2Ah 6Ah 2Bh ...
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Value RAM Index 20h- 3Fh or 60h - 7Fh (auto-increment), continued Address A6-A0 Address A6-A0 with Auto-Increment 36h 76h 37h 77h 38h 78h 39h 79h 3Ah 7Ah 3Bh 7Bh 3Ch 7Ch 3Dh 7Dh 3E- 3Fh 7E- 7Fh Setting all ...
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Reserved - Index 4Bh W83697HF/F Publication Release Date: Feb. 2002 - 107 - Revision 0.70 ...
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SMI#/OVT# Property Select Register- Index 4Ch Register Location: Power on Default Value Attribute: Size: 7 Bit 7: Reserved. User Defined. Bit6: Set to 1, the SMI# output type of Temperature 2(VTIN2) is set to Comparator Interrupt mode. Set to ...
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Bit 7~4: Reserved. Bit 3: FAN 2 output value if FANINC2 sets to 0. Write 1, then pin 113 always generate logic high signal. Write 0, pin 113 always generates logic low signal. This bit default 0. Bit 2: ...
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W83697HF/F Publication Release Date: Feb. 2002 - 110 - Revision 0.70 ...
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Winbond Vendor ID Register - Index 4Fh (No Auto Increase) Register Location: Power on Default Value Attribute: Size: 15 Bit 15-8: Vendor ID High Byte if CR4E.bit7=1.Default 5Ch. Bit 7-0: Vendor ID Low Byte if CR4E.bit7=0. Default A3h. 9.7.18 ...
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Bit 5: Enable BEEP Output from Temperature Sensor 2 if the monitor value exceed the limit value. Write 1, enable BEEP output. Default 0 W83697HF/F Publication Release Date: Feb. 2002 - 112 - Revision 0.70 ...
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Bit 4: Enable BEEP output for Temperature Sensor 1 if the monitor value exceed the limit value. Write 1, enable BEEP output. Default 0 Bit 3: Enable BEEP output from AVCC (+5V), Write 1, enable BEEP output if the monitor ...
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Chip ID -- Index 58h ( Bank 0 ) Register Location: Power on Default Value Attribute: Size Bit 7: Winbond Chip ID number. Read this register will return 60h. 9.7.22 Reserved Register -- Index 59h ( Bank ...
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Reserved -- Index 5Ah ( Bank 0 ) 9.7.24 Reserved -- Index 5Bh ( Bank 0 ) 9.7.25 Reserved -- Index 5Ch ( Bank 0 ) 9.7.26 VBAT Monitor Control Register -- Index 5Dh ( Bank 0 ) Register ...
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Reserved Register -- 9.7.28 Reserved Register -- 9.7.29 Temperature Sensor 2 Temperature (High Byte) Register - Index 50h ( Bank 1 ) Register Location: 50h Attribute: Read Only Size: 8 bits 7 6 Bit 7: Temperature <8:1> of sensor ...
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Temperature Sensor 2 Configuration Register - Index 52h ( Bank 1 ) Register Location: Power on Default Value Size: 7 Bit 7-5: Read - Reserved. This bit should be set to 0. Bit 4-3: Read/Write - Number of faults ...
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Temperature Sensor 2 Hysteresis (Low Byte) Register - Index 54h ( Bank 1 ) Register Location: Power on Default Value 00h Attribute: Size: 7 Bit 7: Hysteresis temperature bit 0, which is low Byte. Bit 6-0: Reserved. 9.7.34 Temperature ...
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Temperature Sensor 2 Over-temperature (Low Byte) Register - Index 56h ( Bank 1 ) Register Location: Power on Default Value 00h Attribute: Size: 7 Bit 7: Over-temperature bit 0, which is low Byte. Bit 6-0: Reserved. 9.7.36 Interrupt Status ...
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SMI# Mask Register 3 -- Index 51h (BANK 4) Register Location: Power on Default Value 00h Attribute: Size: 7 Bit 7-2: Reserved. Bit 1: A one disables the corresponding interrupt status bit for SMI interrupt. Bit 0: A one ...
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Temperature Sensor 1 Offset Register -- Index 54h ( Bank 4 ) Register Location: Power on Default Value Attribute: Size Bit 7-0: Temperature 1 base temperature. The temperature is added by both monitor value and offset value. ...
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Real Time Hardware Status Register I -- Index 59h ( Bank 4 ) Register Location: Power on Default Value 00h Attribute: Size: 7 Bit 7: FAN 2 Status. Set 1, the fan speed counter is over the limit value. ...
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Bit 7-6: Reserved Bit 5: Reserved Bit 4: Case Open Status. Set 1, the case open sensor is sensed the high value. Set 0 Bit 3: Reserved Bit 2: -5V Voltage Status. Set 1, the voltage of -5V is ...
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Reserved Register -- Index 5Ch ( Bank 4 ) 9.7.47 Reserved Register -- Index 5Dh ( Bank 4 ) Index 50h - 5Ah (auto-increment) (BANK 5) 9.7.48 Value RAM 2 Address A6-A0 Auto-Increment 50h 5VSB reading 51h VBAT reading ...
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FAN 1 Duty Cycle Select Register-- 01h ( Bank 0 ) Power on default [7:0] 1111,1111 b Bit Name 7-0 F1_DC[7:0] Read/Write 9.7.52 FAN 2 Pre-Scale Register-- Index 02h Power on default [7:0] = 0000,0001 b Bit Name 7 ...
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FAN2 Duty Cycle Select Register-- Index 03h Power on default [7:0] = 1111,1111 b Bit Name 7-0 F2_DC[7:0] Read/Write 9.7.54 FAN Configuration Register-- Index 04h Power on default [7:0] = 0000,0000 b Bit Name 7-2 Reserved 5-4 FAN2_MODE 3-2 ...
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W83697HF/F Publication Release Date: Feb. 2002 - 127 - Revision 0.70 ...
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VTIN1 Target Temperature Register/ Fan 1 Target Speed Register -- Index 05h Power on default [7:0] = 0000,0000 b CPUT1 target temperature register for Thermal Cruise mode. Bit Name 7 Reserved 6-0 TEMP_TAR_T1[6:0] Fan 1 target speed register for ...
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Tolerance of Target Temperature or Target Speed Register -- Index 07h Power on default [7:0] = 0001,0001 b Tolerance of CPUT1/CPUT2 target temperature register. Bit Name 7-4 TOL_T2[3:0] Read/Write 3-0 TOL_T1[3:0] Read/Write Tolerance of Fan 1/2 target speed register. ...
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Fan 1 Start-up Duty Cycle Register -- Index 0Ah Power on default [7:0] = 0000,0001 b Bit Name 7-0 START_DC1[7:0] Read/Write 9.7.61 Fan 2 Start-up Duty Cycle Register -- Index 0Bh Power on default [7:0] = 0000,0001 b Bit ...
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Fan Step Down Time Register -- Index 0Eh Power on defualt [7:0] = 0000,1010 b Bit Name 7-0 STEP_UP_T[7:0] Read/Write 9.7.65 Fan Step Up Time Register -- Index 0Fh Power on default [7:0] = 0000,1010 b Bit Name 7-0 ...
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CONFIGURATION REGISTER 10.1 Plug and Play Configuration The W83697HF uses Compatible PNP protocol to access configuration registers for setting up different types of configurations. In W83697HF, there are eleven Logical Devices (from Logical Device 0 to Logical Device B ...
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After Power-on reset, the value on RTSA# (pin 49) is latched by HEFRAS of CR26. In Compatible PnP, a specific value (87h) must be written twice to the Extended Functions Enable Register (I/O port address 2Eh or 4Eh). Secondly, an ...
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Configuration Sequence To program W83697HF configuration registers, the following configuration sequence must be followed: (1). Enter the extended function mode (2). Configure the configuration registers (3). Exit the extended function mode 10.3.1 Enter the extended function mode To place ...
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Enter the extended function mode ,interruptible double-write ;----------------------------------------------------------------------------------- MOV DX,2EH MOV AL,87H OUT DX,AL OUT DX,AL ;----------------------------------------------------------------------------- ; Configurate logical device 1, configuration register CRF0 | ;----------------------------------------------------------------------------- MOV DX,2EH MOV AL,07H OUT DX,AL ; point to Logical Device ...
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Chip (Global) Control Register CR02 (Default 0x00) Bit Reserved. Bit 0 : SWRST --> Soft Reset. CR07 Bit LDNB7 - LDNB0 --> Logical Device Number Bit CR20 Bit ...
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CR23 (Default 0x00) Bit Reserved. Bit 0 : IPD (Immediate Power Down). When set will put the whole chip into power down mode immediately. CR24 (Default 0x00) Bit 7 : Reserved. Bit 6 ...
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CR26 (Default 0x00) Bit 7 : SEL4FDD = 0 Select two FDD mode Select four FDD mode Bit 6 : HEFRAS These two bits define how to enable Configuration mode. The corresponding power-on setting pin is RTSA #(pin ...
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CR28 (Default 0x00) Bit Reserved. Bit PRTMODS2 - PRTMODS0 = 0xx Parallel Port Mode = 100 Reserved = 101 External FDC Mode = 110 Reserved = 111 External two FDC Mode CR29 ...
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Bit 5 : (PIN & 76 ~77 GPIO Fresh IF (XA!5 ~ XA10 & XA7 ~ A0) Bit 4 : (PIN & 97 GPIO 5(GP52 ...
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CRF0 (Default 0x0E) FDD Mode Register Bit 7 : FIPURDWN This bit controls the internal pull-up resistors of the FDC input pins RDATA, INDEX, TRAK0, DSKCHG, and WP The internal pull-up resistors of FDC are turned on.(Default) = ...
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Bit Density Select = 00 Normal (Default Normal = Forced to logic Forced to logic 0) Bit 1 : DISFDDWR = 0 Enable FDD write. = ...
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TABLE A Drive Rate Table Select DRTS1 DRTS0 DRATE1 TABLE B DTYPE0 DTYPE1 DRVDEN0(pin ...
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Logical Device 1 (Parallel Port) CR30 (Default 0x01 if PNPCSV = 0 during POR, default 0x00 otherwise) Bit Reserved. Bit Activates the logical device Logical device is inactive. CR60, CR ...
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Logical Device 2 (UART A) CR30 (Default 0x01 if PNPCSV = 0 during POR, default 0x00 otherwise) Bit Reserved. Bit Activates the logical device Logical device is inactive. CR60, CR ...
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CRF0 (Default 0x00) Bit Reserved. Bit 3 : RXW4C = 0 No reception delay when SIR is changed from TX mode to RX mode Reception delays 4 characters-time (40 bit-time) when SIR is changed ...
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Bit 2 : HDUPLX. IR half/full duplex function select The IR function is Full Duplex The IR function is Half Duplex. Bit 1 : TX2INV the SOUTB pin of UART B function or IRTX ...
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CR62 (Default 0x00, 0x00) These two registers select the GPIO1 base address [0x100:0xFFF byte boundary IO address : CRF1 base address CRF0 (GP10-GP17 I/O selection register. Default 0xFF) When set to a '1', respective GPIO port ...
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CR70 (Default 0x09 if PNPCSV = 0 during POR, default 0x00 otherwise) Bit Reserved. Bit [3:0] : These bits select IRQ resource for MIDI Port . CRF0 (GP5 selection register. Default 0xFF) When set to a ...
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CRF4 (Default 0x00) Watch Dog Timer Time-out value. Writing a non-zero value to this register causes the counter to load the value to Watch Dog Counter and start counting down. Reading this register returns current value in Watch Dog Counter ...
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CRF0 (GP2 I/O selection register. Default 0xFF ) When set to a '1', respective GPIO port is programmed as an input port. When set to a '0', respective GPIO port is programmed as an output port. CRF1 (GP2 data register. ...
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Logical Device A (ACPI) CR30 (Default 0x00) Bit Reserved. Bit Activates the logical device Logical device is inactive. CR70 (Default 0x00) Bit Reserved. Bit ...
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CRE7 (Default 0x00) Bit Reserved. Bit 2 :Reset CIR Power-On function. After using CIR power-on, the software should write logical 1 to restart CIR power-on function. Bit 1 : Invert RX Data Inverting RX ...
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CRF1 (Default 0x00) Bit 7 : WAK_STS. This bit is set when the chip is in the sleeping state and an enabled resume event occurs. Upon setting this bit, the sleeping/working state machine will transition the system to the working ...
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CRF6 (Default 0x00) Bit 7~4 : Reserved. Return zero when read. Bit 3~0 : Enable bits of the These bits enable the generation of an SMI / PME SMI / logic output = (PRTIRQEN and PRTIRQSTS) or (FDCIRQEN and FDCIRQSTS) ...
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Bit 1 : CIRIRQEN disable the generation of an SMI / = 1 enable the generation of an SMI / Bit 0 : MIDIIRQEN disable the generation of an SMI / = 1 enable the generation ...
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ORDERING INSTRUCTION PART NO. W83697HF 12 HOW TO READ THE TOP MARKING Example: The top marking of W83697HF inbond inbond inbond W83697HF W83697HF 921A2B282012345 921A2B282012345 1st line: Winbond logo 2nd line: the type number: W83697HF 3th line: the tracking ...
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PACKAGE DIMENSIONS (128-pin PQFP See Detail F y Seating Plane Headquarters No. 4, Creation Rd. III Science-Based Industrial Park Hsinchu, ...