W83697HFFDC Information Storage Devices, Inc, W83697HFFDC Datasheet - Page 82

• Manufacturer Part Number: W83697HFFDC
• Description: LPC Interface I/o Plus Game/midi Port, Fan Control, Flash ROM I/f
• Manufacturer: Information Storage Devices, Inc

6.3.5 cFifo (Parallel Port Data FIFO) Mode = 010
This mode is defined only for the forward direction. The standard parallel port protocol is used by a
hardware handshake to the peripheral to transmit bytes written or DMAed from the system to this FIFO.
Transfers to the FIFO are byte aligned.
6.3.6 ecpDFifo (ECP Data FIFO) Mode = 011
When the direction bit is 0, bytes written or DMAed from the system to this FIFO are transmitted by a
hardware handshake to the peripheral using the ECP parallel port p rotocol. Transfers to the FIFO are
byte aligned.
When the direction bit is 1, data bytes from the peripheral are read under automatic hardware handshake
from ECP into this FIFO. Reads or DMAs from the FIFO will return bytes of ECP data to the system.
6.3.7 tFifo (Test FIFO Mode) Mode = 110
Data bytes may be read, written, or DMAed to or from the system to this FIFO in any direction. Data in
the tFIFO will not be transmitted to the parallel port lines. However, data in the tFIFO may be displayed
on the parallel port data lines.
6.3.8 cnfgA (Configuration Register A) Mode = 111
This register is a read -only register. When it is read, 10H is returned. This indicates to the system that
this is an 8-bit implementation.
6.3.9
The bit definitions are as follows:
Bit 7: This bit is read -only. It is at low level during a read. This means that this chip does not support
Bit 6: Returns the value on the ISA IRQ line to determine possible conflicts.
hardware RLE compression.
cnfgB (Configuration Register B) Mode = 111
7
6
5
4
- 73 -
3
1
2
1
1
1
0
IRQx 0
IRQx 1
IRQx 2
intrValue
compress
Publication Release Date: Feb. 2002
W83697HF/F
Revision 0.70