W83697HFFDC Information Storage Devices, Inc, W83697HFFDC Datasheet - Page 55

• Manufacturer Part Number: W83697HFFDC
• Description: LPC Interface I/o Plus Game/midi Port, Fan Control, Flash ROM I/f
• Manufacturer: Information Storage Devices, Inc

4.
4.1
The UARTs are used to convert parallel data into serial format on the transmit side and convert serial
data to pa rallel format on the receiver side. The serial format, in order of transmission and reception, is
a start bit, followed by five to eight data bits, a parity bit (if programmed) and one, one and half (five-bit
format only) or two stop bits. The UARTs are capable of handling divisors of 1 to 65535 and producing a
16x clock for driving the internal transmitter logic. Provisions are also included to use this 16x clock to
drive the receiver logic. The UARTs also support the MIDI data rate. Furthermore, the UARTs also
include complete modem control capability and a processor interrupt system that may be software
trailed to the computing time required to handle the communication link. The UARTs have a FIFO mode
to reduce the number of interrupts presented to the CPU. In each UART, there are 16-byte FIFOs for
both receive and transmit mode.
4.2
4.2.1 UART Control Register (UCR) (Read/Write)
The UART Control Register controls and defines the protocol for asynchronous data communications,
including data length, stop bit, parity, and baud rate selection.
Bit 7: BDLAB. When this bit is set to a logical 1, designers can access the divisor (in 16-bit binary
Bit 6: SSE. A logical 1 forces the Serial Output (SOUT) to a silent state (a logical 0). Only IRTX is
Bit 5: PBFE. When PBE and PBFE of UCR are both set to a logical 1,
format) from the divisor latches of the baudrate generator during a read or write operation. When
this bit is reset, the Receiver Buffer Register, the Transmitter Buffer Register, or the Interrupt
Control Register can be accessed.
affected by this bit; the transmitter is not affected.
(1) if EPE is logical 1, the parity bit is fixed as logical 0 to transmit and check.
(2) if EPE is logical 0, the parity bit is fixed as logical 1 to transmit and check.
UART PORT
Universal Asynchronous Receiver/Transmitter (UART A, UART B)
Register Address
7
6
5
4
3
2
1
0
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Data length select bit 0 (DLS0)
Data length select bit 1(DLS1)
Multiple stop bits enable (MSBE)
Parity bit enable (PBE)
Even parity enable (EPE)
Parity bit fixed enable (PBFE)
Set silence enable (SSE)
Baudrate divisor latch access bit (BDLAB)
Publication Release Date: Feb. 2002
W83697HF/F
Revision 0.70