MAX9850ETI+T Maxim Integrated Products, MAX9850ETI+T Datasheet - Page 30

• Manufacturer Part Number: MAX9850ETI+T
• Description: IC AMP AUDIO .095W STER 28TQFN
• Manufacturer: Maxim Integrated Products
• Series: DirectDrive™r
• Type: Class ABr

Specifications of MAX9850ETI+T

• Output Type: Headphones, 2-Channel (Stereo)
• Max Output Power X Channels @ Load: 95mW x 2 @ 16 Ohm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Features: DAC, Depop, Digital Inputs, I²C, I²S, Line Level Inputs & Outputs, Mute, Shutdown, Volume Control
• Mounting Type: Surface Mount
• Package / Case: 28-WQFN Exposed Pad, 28-HWQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SDA and SCL idle high when the bus is not in use. A
master initiates communication by issuing a START con-
dition. A START condition is a high-to-low transition on
SDA with SCL high. A STOP condition is a low-to-high
transition on SDA while SCL is high (Figure 6). A START
condition from the master signals the beginning of a
transmission to the MAX9850. The master terminates
transmission, and frees the bus, by issuing a STOP con-
dition. The bus remains active if a REPEATED START
condition is generated instead of a STOP condition.
The MAX9850 recognizes a STOP condition at any point
during data transmission except if the STOP condition
occurs in the same high pulse as a START condition. For
proper operation, do not send a STOP condition during
the same SCL high pulse as the START condition.
Stereo Audio DAC with DirectDrive
Headphone Amplifier
Figure 6. START, STOP, and REPEATED START Conditions
Figure 7. Acknowledge
30
SDA
SCL
SCL
SDA
______________________________________________________________________________________
CONDITION
START
S
1
2
Start and Stop Conditions
Sr
Early STOP Conditions
NOT ACKNOWLEDGE
ACKNOWLEDGE
8
ACKNOWLEDGMENT
CLOCK PULSE FOR
P
9
The MAX9850 is programmable to one of three slave
addresses (see Table 23). These slave addresses are
unique device IDs. Connect ADD to GND, AV
SDA to set the I
defined as the seven most significant bits (MSBs) fol-
lowed by the Read/Write bit. Set the Read/Write bit to 1
to configure the MAX9850 to read mode. Set the
Read/Write bit to 0 to configure the MAX9850 to write
mode. The address is the first byte of information sent to
the MAX9850 after the START condition.
The acknowledge bit (ACK) is a clocked 9th bit that the
MAX9850 uses to handshake receipt of each byte of
data when in write mode (see Figure 7). The MAX9850
pulls down SDA during the entire master-generated 9th
clock pulse if the previous byte is successfully
received. Monitoring ACK allows for detection of unsuc-
cessful data transfers. An unsuccessful data transfer
occurs if a receiving device is busy or if a system fault
has occurred. In the event of an unsuccessful data
transfer, the bus master may retry communication.
The master pulls down SDA during the 9th clock cycle to
acknowledge receipt of data when the MAX9850 is in
read mode. An acknowledge is sent by the master after
each read byte to allow data transfer to continue. A not-
acknowledge is sent when the master reads the final byte
of data from the MAX9850, followed by a STOP condition.
Table 23. MAX9850 Address Map
X = Don’t Care.
AV
ADD
GND
SDA
DD
A6
0
0
0
A5
0
0
0
2
MAX9850 SLAVE ADDRESS
C slave address. The address is
A4
1
1
1
A3
0
0
0
A2
0
0
0
A1
Slave Address
0
0
1
Acknowledge
A0
0
1
1
DD
R/W
, or
X
X
X