MAX9850ETI+T Maxim Integrated Products, MAX9850ETI+T Datasheet - Page 32

• Manufacturer Part Number: MAX9850ETI+T
• Description: IC AMP AUDIO .095W STER 28TQFN
• Manufacturer: Maxim Integrated Products
• Series: DirectDrive™r
• Type: Class ABr

Specifications of MAX9850ETI+T

• Output Type: Headphones, 2-Channel (Stereo)
• Max Output Power X Channels @ Load: 95mW x 2 @ 16 Ohm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Features: DAC, Depop, Digital Inputs, I²C, I²S, Line Level Inputs & Outputs, Mute, Shutdown, Volume Control
• Mounting Type: Surface Mount
• Package / Case: 28-WQFN Exposed Pad, 28-HWQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The address pointer can be preset to a specific register
before a read command is issued. The master presets
the address pointer by first sending the MAX9850’s
slave address with the R/W bit set to 0 followed by the
register address. A REPEATED START condition is then
sent followed by the slave address with the R/W bit set
to 1. The MAX9850 transmits the contents of the speci-
fied register. The address pointer autoincrements after
transmitting the first byte. Attempting to read from reg-
ister addresses higher than 0xB results in repeated
reads of 0xB. Note that 0xB is a reserved register.
The master acknowledges receipt of each read byte
during the acknowledge clock pulse. The master must
acknowledge all correctly received bytes except the
last byte. The final byte must be followed by a not-
acknowledge from the master and then a STOP condi-
tion. Figure 10 illustrates the frame format for reading
one byte from the MAX9850. Figure 11 illustrates the
frame format for reading multiple bytes from the
MAX9850.
The MAX9850 powers on in low-power shutdown mode
with the DAC, headphones, line inputs, and outputs all
disabled. For useful circuit operation to be available,
the charge pump needs to be activated using
CPEN(1:0) in the enable register (register 0x5, bits B5
Stereo Audio DAC with DirectDrive
Headphone Amplifier
Figure 10. Reading One Byte of Data from MAX9850
Figure 11. Reading n-Bytes from MAX9850
32
S
______________________________________________________________________________________
S
ACKNOWLEDGE FROM MAX9850
SLAVE ADDRESS
ACKNOWLEDGE FROM MAX9850
SLAVE ADDRESS
Applications Information
Powering On/Off the MAX9850
R/W
0
R/W
A
ACKNOWLEDGE FROM MAX9850
0
REGISTER ADDRESS
A
ACKNOWLEDGE FROM MAX9850
REPEATED START
REGISTER ADDRESS
A
Sr
REPEATED START
ACKNOWLEDGE FROM MAX9850
SLAVE ADDRESS
A
Sr
ACKNOWLEDGE FROM MAX9850
R/W
and B4). Setting the appropriate bits in the enable reg-
ister will enable the desired circuit functions on the
MAX9850. Finally, the global shutdown bit, SHDN
needs to be set to 1 (register 0x5, bit B7). The enable
bits can all be set with a single I
It is good practice for an application to configure the
I
down. This may include setting initial volume levels,
DAC mode of operation, stereo or mono operation, and
audio interface settings. Powering on the MAX9850 with
all the registers set ensures that the audio output will
not be interrupted.
The charge pump starts and establishes the internal
supply voltages once the appropriate byte is written to
the enable register. The MAX9850 is ready for opera-
tion approximately 10ms after the charge pump is
enabled. If selected, the headphone outputs will also
complete a clickless/popless power-up sequence dur-
ing this time. The headphone amplifier status bit (SHP)
(register 0x1, bit B3) sets to 1 once the headphones
are ready to operate. The line inputs and outputs will
also turn on during this 10ms startup period if enabled.
Let AC-coupling capacitors settle before enabling the line
input amplifiers. The input-coupling capacitor charges to
the output bias voltage of the driving device even while
the MAX9850 is in shutdown. The input AC coupling
capacitors are charged and ready for use immediately
after power is applied to the system in most applications.
2
C registers before taking the MAX9850 out of shut-
SLAVE ADDRESS
1
A
ACKNOWLEDGE FROM MASTER
B7 B6
FIRST DATA BYTE
B5 B4
1 BYTE
REGISTER ADDRESS POINTER
AUTOINCREMENT INTERNAL
R/W
B3 B2
1
B1 B0
NOT ACKNOWLEDGE FROM MASTER
A
B7 B6
A
B5 B4
B7 B6
DATA BYTE
2
1 BYTE
REGISTER ADDRESS POINTER
C write operation.
AUTOINCREMENT INTERNAL
B5 B4
B3 B2
Nth DATA WORD
NOT ACKNOWLEDGE
1 BYTE
REGISTER ADDRESS POINTER
FROM MASTER
AUTOINCREMENT INTERNAL
B3 B2
B1 B0
B1 B0
A
A
P
P