MAX9888EWY+T Maxim Integrated Products, MAX9888EWY+T Datasheet
MAX9888EWY+T
Specifications of MAX9888EWY+T
Related parts for MAX9888EWY+T
MAX9888EWY+T Summary of contents
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... ADC dynamic range. The device is fully specified over the -40NC to +85NC extended temperature range. DirectDrive is a registered trademark and FLEXSOUND is a trademark of Maxim Integrated Products, Inc. LINEIN A1 LINEIN A2 LINEIN B1 LINEIN B2 _______________________________________________________________ Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’ ...
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Stereo Audio CODEC with FLEXSOUND Technology General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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TABLE OF CONTENTS (continued) ADC Record Level Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Stereo Audio CODEC with FLEXSOUND Technology TABLE OF CONTENTS (continued) Battery Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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FLEXSOUND Technology SDIN2 SDOUT2 LRCLK2 BCLK2 SDIN1 SDOUT1 LRCLK1 BCLK1 Stereo Audio CODEC Functional Diagram 5 ...
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Stereo Audio CODEC with FLEXSOUND Technology ABSOLUTE MAXIMUM RATINGS (Voltages with respect to AGND.) DVDD, AVDD, HPVDD .........................................-0.3V to +2.2V SPKLVDD, SPKRVDD, DVDDS1, DVDDS2 ..........-0.3V to +6.0V DGND, HPGND, SPKLGND, SPKRGND ..............-0.1V to +0.1V HPVSS ............................... (HPGND - 2.2V) to ...
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ELECTRICAL CHARACTERISTICS (continued AVDD HPVDD DVDD DVDDS1 between SPK_P and SPK_N. Receiver load (R HPL or HPR to GND REC = 1FF +20dB, ...
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Stereo Audio CODEC with FLEXSOUND Technology ELECTRICAL CHARACTERISTICS (continued AVDD HPVDD DVDD DVDDS1 between SPK_P and SPK_N. Receiver load (R HPL or HPR to GND ...
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ELECTRICAL CHARACTERISTICS (continued AVDD HPVDD DVDD DVDDS1 between SPK_P and SPK_N. Receiver load (R HPL or HPR to GND REC = 1FF +20dB, ...
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Stereo Audio CODEC with FLEXSOUND Technology ELECTRICAL CHARACTERISTICS (continued AVDD HPVDD DVDD DVDDS1 between SPK_P and SPK_N. Receiver load (R HPL or HPR to GND ...
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ELECTRICAL CHARACTERISTICS (continued AVDD HPVDD DVDD DVDDS1 between SPK_P and SPK_N. Receiver load (R HPL or HPR to GND REC = 1FF +20dB, ...
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Stereo Audio CODEC with FLEXSOUND Technology ELECTRICAL CHARACTERISTICS (continued AVDD HPVDD DVDD DVDDS1 between SPK_P and SPK_N. Receiver load (R HPL or HPR to GND ...
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ELECTRICAL CHARACTERISTICS (continued AVDD HPVDD DVDD DVDDS1 between SPK_P and SPK_N. Receiver load (R HPL or HPR to GND REC = 1FF +20dB, ...
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Stereo Audio CODEC with FLEXSOUND Technology ELECTRICAL CHARACTERISTICS (continued AVDD HPVDD DVDD DVDDS1 between SPK_P and SPK_N. Receiver load (R HPL or HPR to GND ...
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ELECTRICAL CHARACTERISTICS (continued AVDD HPVDD DVDD DVDDS1 between SPK_P and SPK_N. Receiver load (R HPL or HPR to GND REC = 1FF +20dB, ...
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Stereo Audio CODEC with FLEXSOUND Technology ELECTRICAL CHARACTERISTICS (continued AVDD HPVDD DVDD DVDDS1 between SPK_P and SPK_N. Receiver load (R HPL or HPR to GND ...
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ELECTRICAL CHARACTERISTICS (continued AVDD HPVDD DVDD DVDDS1 between SPK_P and SPK_N. Receiver load (R HPL or HPR to GND REC = 1FF +20dB, ...
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Stereo Audio CODEC with FLEXSOUND Technology ELECTRICAL CHARACTERISTICS (continued AVDD HPVDD DVDD DVDDS1 between SPK_P and SPK_N. Receiver load (R HPL or HPR to GND ...
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ELECTRICAL CHARACTERISTICS (continued AVDD HPVDD DVDD DVDDS1 between SPK_P and SPK_N. Receiver load (R HPL or HPR to GND REC = 1FF +20dB, ...
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Stereo Audio CODEC with FLEXSOUND Technology DIGITAL INPUT/OUTPUT CHARACTERISTICS (continued AVDD HPVDD DVDD DVDDS1 otherwise noted. Typical values are at T PARAMETER SYMBOL BCLKS1, LRCLKS1, SDOUTS1—OUTPUT Output Low Voltage V OL Output High ...
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DIGITAL INPUT/OUTPUT CHARACTERISTICS (continued AVDD HPVDD DVDD DVDDS1 otherwise noted. Typical values are at T PARAMETER SYMBOL DIGMICCLK—OUTPUT Output Low Voltage V OL Output High Voltage V OH INPUT CLOCK CHARACTERISTICS (V = ...
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Stereo Audio CODEC with FLEXSOUND Technology AUDIO INTERFACE TIMING CHARACTERISTICS ( AVDD HPVDD DVDD DVDDS1 noted. Typical values are +25NC.) (Note 1) A PARAMETER SYMBOL BCLK Cycle Time t BCLK High ...
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F BCLK (OUTPUT) t CLKSYNC LRCLK (OUTPUT) t CLKTX t HIZOUT SDOUT (OUTPUT) LSB HI-Z SDIN (INPUT) LSB MASTER MODE Figure 2. TDM Audio Interface Timing Diagram (TDM_ = 1, FSW_ = BCLK (OUTPUT) t ENDSYNC ...
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Stereo Audio CODEC with FLEXSOUND Technology Figure 4. Digital Microphone Timing Diagram TIMING CHARACTERSTICS ( AVDD HPVDD DVDD DVDDS1 otherwise noted. Typical values are at T PARAMETER SYMBOL Serial-Clock Frequency Bus ...
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SDA t SU,DAT t LOW t SCL HIGH t HD,STA t R START CONDITION 2 Figure Interface Timing Diagram Note 1: The IC is 100% production tested at T Note 2: Analog supply current = I AVDD ...
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Stereo Audio CODEC with FLEXSOUND Technology ( AVDD HPVDD DVDD DVDDS1 MODE DAC Playback 48kHz Stereo HP DAC à HP 24-bit, music filters, EQ enabled DAC Playback 48kHz Stereo HP DAC à HP 24-bit, ...
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AVDD HPVDD DVDD DVDDS1 MODE Microphone Mono Record 48kHz MIC1/2 à ADC 16-bit, music filters Microphone Mono Record 8kHz MIC1/2 à ADC 16-bit, voice filters Microphone Mono Record 8kHz MIC1/2 à ADC 16-bit, ...
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Stereo Audio CODEC with FLEXSOUND Technology ( AVDD HPVDD DVDD DVDDS1 between SPK_P and SPK_N. Receiver load (R HPL or HPR to GND REC = 1FF. ...
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AVDD HPVDD DVDD DVDDS1 between SPK_P and SPK_N. Receiver load (R HPL or HPR to GND REC = 1FF +20dB, AV MICPRE_ MICPGA_ ...
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Stereo Audio CODEC with FLEXSOUND Technology ( AVDD HPVDD DVDD DVDDS1 between SPK_P and SPK_N. Receiver load (R HPL or HPR to GND REC = 1FF. ...
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AVDD HPVDD DVDD DVDDS1 between SPK_P and SPK_N. Receiver load (R HPL or HPR to GND REC = 1FF +20dB, AV MICPRE_ MICPGA_ ...
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Stereo Audio CODEC with FLEXSOUND Technology ( AVDD HPVDD DVDD DVDDS1 between SPK_P and SPK_N. Receiver load (R HPL or HPR to GND REC = 1FF. ...
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AVDD HPVDD DVDD DVDDS1 between SPK_P and SPK_N. Receiver load (R HPL or HPR to GND REC = 1FF +20dB, AV MICPRE_ MICPGA_ ...
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Stereo Audio CODEC with FLEXSOUND Technology ( AVDD HPVDD DVDD DVDDS1 between SPK_P and SPK_N. Receiver load (R HPL or HPR to GND REC = 1FF. ...
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AVDD HPVDD DVDD DVDDS1 between SPK_P and SPK_N. Receiver load (R HPL or HPR to GND REC = 1FF +20dB, AV MICPRE_ MICPGA_ ...
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Stereo Audio CODEC with FLEXSOUND Technology ( AVDD HPVDD DVDD DVDDS1 between SPK_P and SPK_N. Receiver load (R HPL or HPR to GND REC = 1FF +20dB, ...
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AVDD HPVDD DVDD DVDDS1 between SPK_P and SPK_N. Receiver load (R HPL or HPR to GND REC = 1FF +20dB, AV MICPRE_ MICPGA_ ...
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Stereo Audio CODEC with FLEXSOUND Technology ( AVDD HPVDD DVDD DVDDS1 between SPK_P and SPK_N. Receiver load (R HPL or HPR to GND REC = 1FF. ...
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AVDD HPVDD DVDD DVDDS1 between SPK_P and SPK_N. Receiver load (R HPL or HPR to GND REC = 1FF +20dB, AV MICPRE_ MICPGA_ ...
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Stereo Audio CODEC with FLEXSOUND Technology ( AVDD HPVDD DVDD DVDDS1 between SPK_P and SPK_N. Receiver load (R HPL or HPR to GND REC = 1FF. ...
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AVDD HPVDD DVDD DVDDS1 between SPK_P and SPK_N. Receiver load (R HPL or HPR to GND REC = 1FF +20dB, AV MICPRE_ MICPGA_ ...
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Stereo Audio CODEC with FLEXSOUND Technology ( AVDD HPVDD DVDD DVDDS1 between SPK_P and SPK_N. Receiver load (R HPL or HPR to GND REC = 1FF. ...
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AVDD HPVDD DVDD DVDDS1 between SPK_P and SPK_N. Receiver load (R HPL or HPR to GND REC = 1FF +20dB, AV MICPRE_ MICPGA_ ...
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Stereo Audio CODEC with FLEXSOUND Technology ( AVDD HPVDD DVDD DVDDS1 between SPK_P and SPK_N. Receiver load (R HPL or HPR to GND REC = 1FF. ...
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AVDD HPVDD DVDD DVDDS1 between SPK_P and SPK_N. Receiver load (R HPL or HPR to GND REC = 1FF +20dB, AV MICPRE_ MICPGA_ AV = 0dB, ...
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Stereo Audio CODEC with FLEXSOUND Technology ( AVDD HPVDD DVDD DVDDS1 between SPK_P and SPK_N. Receiver load (R HPL or HPR to GND REC = 1FF. ...
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AVDD HPVDD DVDD DVDDS1 between SPK_P and SPK_N. Receiver load (R HPL or HPR to GND REC = 1FF +20dB, AV MICPRE_ MICPGA_ ...
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Stereo Audio CODEC with FLEXSOUND Technology ( AVDD HPVDD DVDD DVDDS1 between SPK_P and SPK_N. Receiver load (R HPL or HPR to GND REC = 1FF. ...
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AVDD HPVDD DVDD DVDDS1 between SPK_P and SPK_N. Receiver load (R HPL or HPR to GND REC = 1FF +20dB, AV MICPRE_ MICPGA_ ...
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Stereo Audio CODEC with FLEXSOUND Technology TOP VIEW (BUMP SIDE DOWN SPKRN SPKRGND SPKLVDD A SPKRN SPKRGND SPKLVDD B SPKRP SPKRP SPKRVDD C D BCLKS1 LRCLKS1 SPKRVDD E DVDDS1 MCLK N.C. DGND BCLKS2 LRCLKS2 F SDOUTS2 DVDDS2 SDINS2 ...
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PIN NAME A1, B1 SPKRN Negative Right-Channel Class D Speaker Output A2, B2 SPKRGND Right-Speaker Ground Left-Speaker, REF, Receiver Amplifier Power Supply. Bypass to SPKLGND with a 1FF and a 10FF A3, B3 SPKLVDD capacitor. A4, B4 SPKLP Positive Left-Channel ...
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Stereo Audio CODEC with FLEXSOUND Technology PIN NAME E1 DVDDS1 S1 Digital Audio Interface Power-Supply Input. Bypass to DGND with a 1FF capacitor. E2 MCLK Master Clock Input. Acceptable input frequency range is 10MHz to 60MHz. E4 SDOUTS1 S1 Digital ...
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Detailed Description The MAX9888 is a fully integrated stereo audio codec with FLEXSOUND technology and integrated amplifiers. Two differential microphone amplifiers can accept sig- nals from three analog inputs. One input can be retasked to support two digital microphones. Any ...
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Stereo Audio CODEC with FLEXSOUND Technology I 2 Configure the MAX9888 using the I IC uses a slave address of 0x20 or 00100000 for write operations and 0x21 or 00100001 for read operations. See the Serial Interface ...
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Table 1. Register Map (continued) REGISTER Time-Division SLOTL2 Multiplex Filters MIXERS DAC Mixer MIXDAL Left ADC Mixer Right ADC Mixer Preoutput Mixer Preoutput Mixer Preoutput 3 ...
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Stereo Audio CODEC with FLEXSOUND Technology Table 1. Register Map (continued) REGISTER Microphone 0 PA2EN 2 Input Level INA Input 0 INAEXT 0 Level INB Input 0 INBEXT 0 Level Preoutput Level Preoutput ...
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Table 1. Register Map (continued) REGISTER Power Limiter PWRTH Power Limiter PWRT2 Distortion THDCLP Limiter CONFIGURATION Audio Input INADIFF INBDIFF 0 Microphone MICCLK DIGMICL DIGMICR Level Control VS2EN VSEN ZDEN Bypass INABYP 0 0 Switches Jack JDETEN ...
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Stereo Audio CODEC with FLEXSOUND Technology Table 1. Register Map (continued) REGISTER Band 3 (DAI1/DAI2) EQ Band 4 (DAI1/DAI2) EQ Band 5 (DAI1/DAI2) Excursion Limiter Biquad (DAI1/DAI2) REVISION ID Rev ...
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The IC includes comprehensive power management to allow the disabling of all unused circuits, minimizing supply current. Table 2. Power Management Registers REGISTER BIT NAME 7 SHDN 0x4C 6 VBATEN 1 JDWK 7 INAEN 6 INBEN 0x4A 3 MBEN 1 ...
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Stereo Audio CODEC with FLEXSOUND Technology Microphone Inputs The device includes three differential microphone inputs and a low-noise microphone bias for powering the micro- phones (Figure 6). One microphone input can also be con- figured as a digital microphone input ...
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Table 3. Microphone Input Registers REGISTER BIT NAME 6 PA1EN/PA2EN 0x31/0x32 2 PGAM1/PGAM2 MICCLK 6 5 DIGMICL 0x46 4 DIGMICR 1 EXTMIC 0 Stereo Audio CODEC with FLEXSOUND Technology DESCRIPTION MIC1/MIC2 Preamplifier Gain Course ...
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Stereo Audio CODEC with FLEXSOUND Technology Table 3. Microphone Input Registers (continued) REGISTER BIT NAME 7 INABYP 4 MIC2BYP 0x48 1 RECBYP 0 SPKBYP The device includes two sets of line inputs (Figure 7). Each set can be configured as ...
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Table 4. Line Input Registers REGISTER BIT NAME 6 INAEXT/INBEXT 2 0x33/0x34 1 PGAINA/PGAINB 0 7 INADIFF 0x45 6 INBDIFF ADC Input Mixers The device’s stereo ADC accepts input from the micro- phone amplifiers and line inputs. The ADC mixer ...
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Stereo Audio CODEC with FLEXSOUND Technology Table 5. ADC Input Mixer Register REGISTER BIT NAME 0x22/0x23 MIXADL/MIXADR Record Path Signal Processing The device’s record signal path includes both automatic gain control (AGC) ...
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Table 6. Record Path Signal Processing Registers REGISTER BIT NAME 0x01 3 AGC AGCSRC 6 0x3D 5 AGCRLS 4 Stereo Audio CODEC with FLEXSOUND Technology DESCRIPTION Noise Gate Attenuation Reports the ...
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Stereo Audio CODEC with FLEXSOUND Technology Table 6. Record Path Signal Processing Registers (continued) REGISTER BIT NAME 3 AGCATK 2 0x3D 1 AGCHLD ANTH 5 4 0x3E 3 2 AGCTH DESCRIPTION AGC Attack Time ...
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ATTACK TIME Figure 12. AGC Timing ADC Record Level Control The IC includes separate digital level control for the left and right ADC outputs (Figure 13). To optimize dynamic ADLEN ADREN Figure 13. ADC Record Level Control Block Diagram Stereo ...
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Stereo Audio CODEC with FLEXSOUND Technology Table 7. ADC Record Level Control Register REGISTER BIT NAME 5 AVLG/AVRG 4 3 0x2F/0x30 2 AVL/AVR 1 0 Enable sidetone during full-duplex operation to add a low-level copy of the recorded audio signal ...
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Table 8. Sidetone Register REGISTER BIT NAME 7 DSTS 0x2A 2 DVST 1 0 Digital Audio Interfaces The IC includes two separate playback signal paths and one record signal path. Digital audio interface 1 (DAI1) is used ...
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Stereo Audio CODEC with FLEXSOUND Technology data input to either SDINS1 or SDINS2 to be routed from one interface to the other for output on SDOUTS2 or SDOUTS1. Both interfaces must be configured for the same sample rate, but the ...
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Table 10. Digital Audio Interface Registers REGISTER BIT NAME 7 MAS1/MAS2 6 WCI1/WCI2 5 BCI1/BCI2 0x14/0x1C 4 DLY1/DLY2 2 TDM1/TDM2 1 FSW1/FSW2 0 WS1/WS2 Stereo Audio CODEC with FLEXSOUND Technology DESCRIPTION DAI1/DAI2 Master Mode In master mode, DAI1/DAI2 outputs LRCLK ...
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Stereo Audio CODEC with FLEXSOUND Technology Table 10. Digital Audio Interface Registers (continued) REGISTER BIT NAME 7 OSR1 6 2 0x15/0x1D BSEL1/ 1 BSEL2 0 7 SEL1/SEL2 6 5 LTEN1 0x16/0x1E LBEN1/ 4 LBEN2 DMONO1/ 3 DMONO2 72 DESCRIPTION ADC ...
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Table 10. Digital Audio Interface Registers (continued) REGISTER BIT NAME HIZOFF1/ 2 HIZOFF2 0x16/0x1E SDOEN1/ 1 SDOEN2 SDIEN1/ 0 SDIEN2 7 SLOTL1/ SLOTL2 6 5 0x17/0x1F SLOTR1/ SLOTR2 SLOTDLY1/ SLOTDLY2 1 0 Stereo Audio CODEC with FLEXSOUND ...
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Stereo Audio CODEC with FLEXSOUND Technology WCI_ = 0, BCI_ = 0, DLY_ = 0, TDM_ = 0, FSW_ = 0, WS_ = 0, HIZOFF_ = 1, SLOTL_ = 0, SLOTR_ = 0 LRCLK SDOUT D15 D14 D13 D12 D11 ...
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WCI_ = 0, BCI_ = 1, DLY_ = 0, TDM_ = 1, FSW_ = 0, WS_ = 0, HIZOFF_ = 0, SLOTL_ = 0, SLOTR_ = 1 LRCLK SDOUT HI-Z L15 L14 L13 L12 L11 L10 ...
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Stereo Audio CODEC with FLEXSOUND Technology The digital signal paths in the IC require a master clock (MCLK) between 10MHz and 60MHz to func- tion. Internally, the MAX9888 requires a clock between 10MHz and 20MHz. A prescaler divides MCLK by ...
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Table 11. Clock Control Registers (continued) REGISTER BIT NAME 3 2 0x11 FREQ1 1 7 PLL1/PLL2 6 0x12/0x1A NI1/ NI2 0x13/0x1B 1 0 NI1[0]/NI2[0] Stereo Audio CODEC with ...
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Stereo Audio CODEC with FLEXSOUND Technology Table 12. Common NI1/NI2 Values PCLK (MHz) 8 11.025 12 10 13A9 1B18 1D7E 11 11E0 18A2 1ACF 11.2896 116A 1800 1A1F 1062 1694 1893 12 12.288 1000 160D 1800 13 0F20 14D8 16AF ...
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Table 13. Passband Filtering Registers REGISTER BIT NAME 7 MODE1 6 5 AVFLT1 4 0x18 3 DHF1 2 1 DVFLT1 0 3 DHF2 0x20 0 DCB2 Stereo Audio CODEC with FLEXSOUND Technology DESCRIPTION DAI1 Passband Filtering Mode 0 = Voice ...
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Stereo Audio CODEC with FLEXSOUND Technology Table 14. Voice Highpass Filters AVFTL/DVFLT VALUE INTENDED SAMPLE RATE 000 001/011 16kHz/8kHz 010/100 16kHz/8kHz 101 8kHz to 48kHz 110/111 80 N/A -10 -20 -30 -40 -50 -60 -10 -20 -30 -40 -50 -60 ...
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Playback Path Signal Processing The IC playback signal path includes automatic level control (ALC) and a 5-band parametric equalizer (EQ) (Figure 19). The DAI1 and DAI2 playback paths include separate ALCs controlled by a single set of registers. Two completely ...
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Stereo Audio CODEC with FLEXSOUND Technology Table 15. Automatic Level Control Registers REGISTER BIT NAME 7 ALCEN 6 ALCRLS 5 4 0x41 3 ALCMB 2 1 ALCTH 0 Parametric Equalizer The parametric EQ contains five independent biquad filters with programmable ...
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Use the attenuator at the EQ’s input to avoid clipping the signal. The attenuator can be programmed for fixed attenuation or dynamic attenuation based on signal level. If the dynamic EQ clip detection is enabled, the signal level from the ...
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Stereo Audio CODEC with FLEXSOUND Technology Playback Level Control The IC includes separate digital level control for the DAI1 and DAI2 playback audio paths. The DAI1 signal path DV1G: 0/6/12/18dB + MULTIBAND ALC DVEQ1: 0dB TO -15dB 5-BAND PARAMETRIC EQ ...
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The IC’s stereo DAC accepts input from two digital audio paths. The DAC mixer routes any audio path to the left and right DACs (Figure 23). DV1G: 0/6/12/18dB + MULTIBAND ALC DVEQ1: 0dB TO -15dB 5-BAND PARAMETRIC EQ EQ1EN EXCURSION ...
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Stereo Audio CODEC with FLEXSOUND Technology The IC’s preoutput mixer stage provides mixing and level adjustment for line input signals routed to the output ampli- fiers. Figure 24 shows a block diagram of the preoutput signal path. 9dB is added ...
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The IC’s preoutput PGAs allow line input signals to be attenuated to match DAC output signal levels. Use the 0dB setting for maximum performance. Table 20. Preoutput PGA Registers REGISTER BIT NAME 3 2 PGAOUT1/ 0x35/0x36/ PGAOUT2/ 0x37 1 PGAOUT3 ...
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Stereo Audio CODEC with FLEXSOUND Technology The IC’s receiver amplifier accepts input from the stereo DAC and the line inputs. Configure the mixer to mix any combina- tion of the available sources. When more than one signal is selected, the ...
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Speaker Amplifiers The IC integrates a stereo filterless Class D amplifier that offers much higher efficiency than Class AB without the typical disadvantages. The high efficiency of a Class D amplifier is due to the switching operation of the output ...
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Stereo Audio CODEC with FLEXSOUND Technology The IC’s speaker amplifiers accept input from the stereo DAC and the line inputs. Configure the mixer to mix any combina- tion of the available sources. When more than one signal is selected, the ...
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Speaker Amplifier Signal Processing The IC includes signal processing to improve the sound quality of the speaker output and protect transducers from damage. An excursion limiter dynamically adjusts the highpass corner frequency, while a power limiter and distortion limiter prevent ...
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Stereo Audio CODEC with FLEXSOUND Technology Table 25. Excursion Limiter Registers REGISTER BIT NAME Excursion Limiter Corner Frequency 6 The excursion limiter has limited sliding range and minimum corner frequencies. Listed below are all the valid filter combinations. LOWER CORNER ...
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The IC’s power limiter tracks the RMS power delivered to the loudspeaker and briefly mutes the speaker amplifier output if the speaker is at risk of sustaining permanent damage. Loudspeakers are typically damaged when the voice coil overheats due to ...
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Stereo Audio CODEC with FLEXSOUND Technology Table 26. Power Limiter Registers (continued PWRT2 5 4 0x43 3 2 PWRT1 1 0 The IC’s distortion limiter ensures that the speaker amplifier’s output does not exceed the programmed THD+N limit. ...
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Table 27. Distortion Limiter Registers REGISTER BIT NAME 7 6 THDCLP 5 4 0x44 2 1 THDT1 0 Headphone Amplifier The IC’s headphone amplifier integrates Maxim’s DirectDrive architecture to eliminate the need for large DC-blocking capacitors. Traditional single-supply head- phone ...
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Stereo Audio CODEC with FLEXSOUND Technology Alternative approaches to eliminating the output-cou- pling capacitors involve biasing the headphone return (sleeve) to the DC bias voltage of the headphone ampli- fiers. This method raises some issues: U The sleeve is typically ...
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Table 28. Headphone Output Mixer Register REGISTER BIT NAME 7 6 MIXHPL 5 4 0x27 3 2 MIXHPR 1 0 Headphone Output Volume Table 29. Headphone Output Level Register REGISTER BIT NAME 7 HPLM/HPRM 4 3 0x38/0x39 HPVOLL/HPVOLR 2 1 ...
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Stereo Audio CODEC with FLEXSOUND Technology Output Bypass Switches The IC includes two output bypass switches that solve common applications problems. When a single trans- ducer is used for the loudspeaker and receiver, the need exists for two amplifiers to ...
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Click-and-Pop Reduction The IC includes extensive click-and-pop reduction cir- cuitry. The circuitry minimizes clicks and pops at turn-on, turn-off, and during volume changes. Zero-crossing detection is implemented on all analog PGAs and volume controls to prevent large glitches when volume ...
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Stereo Audio CODEC with FLEXSOUND Technology The IC features jack detection that can detect the inser- tion and removal of a jack as well as the load type. When a jack is detected, an interrupt on IRQ can be triggered ...
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The IC detects jack removal by monitoring JACKSNS for transitions to the 11 state. Set JDETEN to enable jack detection circuitry. A pullup current is automatically Table 34. Change in JKSNS Upon Jack Removal JACK TYPE GND GND R L ...
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Stereo Audio CODEC with FLEXSOUND Technology Battery Measurement The IC measures the voltage applied to SPKLVDD (typi- cally the battery voltage) and reports the value in regis- ter 0x03. This value is also used by the speaker limiter Table 36. ...
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The IC uses register 0x00 and IRQ to report the status of various device functions. The status register bits are set when their respective events occur, and cleared upon reading the register. Device status can be determined Table 37. Status ...
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Stereo Audio CODEC with FLEXSOUND Technology Device Revision Table 38. Device Revision Register REGISTER BIT NAME 0xFF REV (Read Only Serial Interface 2 The IC features C/SMBusK-compatible, ...
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The slave address is defined as the seven most signifi- cant bits (MSBs) followed by the read/write bit. For the IC, the seven most significant bits are 0010000. Setting the read/write bit to 1 (slave address = 0x21) configures the ...
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Stereo Audio CODEC with FLEXSOUND Technology The slave address with the R/W bit set to 0 indicates that the master intends to write data to the IC. The IC acknowledges receipt of the address byte during the master-generated 9th SCL ...
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Applications Information Typical Operating Circuits Figures 39 and 40 provide example operating circuits for the IC. The external components shown are the minimum 10kI TO MICROCONTROLLER 10MHz TO 60MHz CLOCK INPUT DIGITAL AUDIO PORT CONTROL PORT ...
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Stereo Audio CODEC with FLEXSOUND Technology 10kI TO MICROCONTROLLER 10MHz TO 60MHz CLOCK INPUT DIGITAL AUDIO PORT CONTROL PORT DATA DIGITAL MIC 1 CLOCK DATA DIGITAL MIC 2 CLOCK 2.2kI JACKSNS HEADSET MICROPHONE LINE INPUT LINE ...
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Filterless Class D Operation Traditional Class D amplifiers require an output filter to recover the audio signal from the amplifier’s output. The filters add cost, increase the solution size of the amplifier, and can decrease efficiency and THD+N performance. The ...
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Stereo Audio CODEC with FLEXSOUND Technology While many configuration options in the IC can be made while the device is operating, some registers should only be adjusted when the corresponding audio path is disabled. Table 40 lists the registers that ...
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Charge-Pump Flying Capacitor The value of the flying capacitor (connected between C1N and C1P) affects the output resistance of the charge pump. A value that is too small degrades the device’s ability to provide sufficient current drive, which leads to ...
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Stereo Audio CODEC with FLEXSOUND Technology Recommended PCB Routing The IC uses a 63-bump WLP package. Figure 42 provides an example of how to connect to all active bumps using 3 layers of the PCB. To ensure uninter- rupted ground ...
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Route microphone signals from the microphone to the differential pair, ensuring that the positive and nega- tive signals follow the same path as closely as possible with equal trace length. When using single-ended micro- phones or other ...
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Stereo Audio CODEC with FLEXSOUND Technology For the latest package outline information and land patterns www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix ...
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... Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 2011 Maxim Integrated Products © ...