MAX9888EWY+T Maxim Integrated Products, MAX9888EWY+T Datasheet - Page 76

• Manufacturer Part Number: MAX9888EWY+T
• Description: IC CODEC AUDIO FLEXSOUND 63WLP
• Manufacturer: Maxim Integrated Products
• Series: DirectDrive®, FLEXSOUND™r
• Type: Class Dr

Specifications of MAX9888EWY+T

• Output Type: 3-Channel with Stereo Headphones
• Max Output Power X Channels @ Load: 1.37W x 2 @ 8 Ohm; 40mW x 2 @ 16 Ohm
• Voltage - Supply: 2.8 V ~ 5.5 V
• Features: Depop, Differential Inputs, I²S, Microphone, Mute, Shutdown
• Mounting Type: Surface Mount
• Package / Case: 63-WLP
• For Use With: MAX9888EVKIT+ - KIT EVALUATION FOR MAX9888
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The digital signal paths in the IC require a master
clock (MCLK) between 10MHz and 60MHz to func-
tion. Internally, the MAX9888 requires a clock between
10MHz and 20MHz. A prescaler divides MCLK by 1, 2,
or 4 to create the internal clock (PCLK). PCLK is used to
clock all portions of the IC.
The MAX9888 includes two digital audio signal paths,
both capable of supporting any sample rate from 8kHz
to 96kHz. Each path is independently configured to allow
different sample rates. To accommodate a wide range
of system architectures, three main clocking modes are
supported:
U PLL Mode: When operating in slave mode, enable
Stereo Audio CODEC
with FLEXSOUND Technology
Table 11. Clock Control Registers
76
REGISTER
0x11/0x19
the PLL to lock onto any LRCLK input. This mode
0x10
BIT
5
4
7
6
5
4
SR1/SR2
PSCLK
NAME
MCLK Prescaler
Generates PCLK, which is used by all internal circuitry.
00 = PCLK disabled
01 = 10MHz P MCLK P 20MHz (PCLK = MCLK)
10 = 20MHz P MCLK P 40MHz (PCLK = MCLK/2)
11 = 40MHz P MCLK P 60MHz (PCLK = MCLK/4)
DAI1/DAI2 Sample Rate
Used by the ALC to correctly set the dual-band crossover frequency and the excursion
limiter to set the predefined corner frequencies.
Clock Control
VALUE
0x0
0x1
0x2
0x3
0x4
0x5
0x6
0x7
SAMPLE RATE
U Normal Mode: This mode uses a 15-bit clock divider
U Exact Integer Mode (DAI1 only): In both master and
Reserved
11.025
requires the least configuration, but provides the
lowest performance. Use this mode to simplify initial
setup or when normal mode and exact integer mode
cannot be used.
to set the sample rate relative to PCLK. This allows
high flexibility in both the PCLK and LRCLK frequen-
cies and can be used in either master or slave mode.
slave modes, common MCLK frequencies (12MHz,
13MHz, 16MHz, and 19.2MHz) can be programmed
to operate in exact integer mode for both 8kHz and
16kHz sample rates. In these modes, the MCLK and
LRCLK rates are selected by using the FREQ1 bits
instead of the NI, and PLL control bits.
22.05
(kHz)
44.1
16
24
32
8
DESCRIPTION
VALUE
0xA
0xB
0xC
0xD
0x8
0x9
0xE
0xF
SAMPLE RATE
Reserved
Reserved
Reserved
Reserved
Reserved
(kHz)
88.2
48
96