MAX9888EWY+T Maxim Integrated Products, MAX9888EWY+T Datasheet - Page 106

• Manufacturer Part Number: MAX9888EWY+T
• Description: IC CODEC AUDIO FLEXSOUND 63WLP
• Manufacturer: Maxim Integrated Products
• Series: DirectDrive®, FLEXSOUND™r
• Type: Class Dr

Specifications of MAX9888EWY+T

• Output Type: 3-Channel with Stereo Headphones
• Max Output Power X Channels @ Load: 1.37W x 2 @ 8 Ohm; 40mW x 2 @ 16 Ohm
• Voltage - Supply: 2.8 V ~ 5.5 V
• Features: Depop, Differential Inputs, I²S, Microphone, Mute, Shutdown
• Mounting Type: Surface Mount
• Package / Case: 63-WLP
• For Use With: MAX9888EVKIT+ - KIT EVALUATION FOR MAX9888
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Stereo Audio CODEC
with FLEXSOUND Technology
The slave address with the R/W bit set to 0 indicates
that the master intends to write data to the IC. The IC
acknowledges receipt of the address byte during the
master-generated 9th SCL pulse.
The second byte transmitted from the master configures
the IC’s internal register address pointer. The pointer
tells the IC where to write the next byte of data. An
acknowledge pulse is sent by the IC upon receipt of the
address pointer data.
The third byte sent to the IC contains the data that is
written to the chosen register. An acknowledge pulse
from the IC signals receipt of the data byte. The address
pointer autoincrements to the next register address after
each received data byte. This autoincrement feature
allows a master to write to sequential registers within
one continuous frame. The master signals the end of
transmission by issuing a STOP condition. Register
addresses greater than 0xC7 are reserved. Do not write
to these addresses.
Send the slave address with the R/W bit set to 1 to initi-
ate a read operation. The IC acknowledges receipt of
its slave address by pulling SDA low during the 9th SCL
clock pulse. A START command followed by a read com-
mand resets the address pointer to register 0x00.
106
Figure 37. Reading One Byte of Data from the IC
Figure 38. Reading n Bytes of Data from the IC
S
S
ACKNOWLEDGE FROM MAX9888
ACKNOWLEDGE FROM MAX9888
SLAVE ADDRESS
SLAVE ADDRESS
R/W
R/W
O
O
A
A
ACKNOWLEDGE FROM MAX9888
ACKNOWLEDGE FROM MAX9888
REGISTER ADDRESS
Read Data Format
REGISTER ADDRESS
REPEATED START
REPEATED START
A
A
Sr
Sr
ACKNOWLEDGE FROM MAX9888
The first byte transmitted from the IC is the content of
register 0x00. Transmitted data is valid on the rising
edge of SCL. The address pointer autoincrements after
each read data byte. This autoincrement feature allows
all registers to be read sequentially within one continu-
ous frame. A STOP condition can be issued after any
number of read data bytes. If a STOP condition is issued
followed by another read operation, the first data byte to
be read is from register 0x00.
The address pointer can be preset to a specific register
before a read command is issued. The master presets
the address pointer by first sending the IC’s slave
address with the R/W bit set to 0 followed by the register
address. A REPEATED START condition is then sent fol-
lowed by the slave address with the R/W bit set to 1. The
IC then transmits the contents of the specified register.
The address pointer autoincrements after transmitting
the first byte.
The master acknowledges receipt of each read byte
during the acknowledge clock pulse. The master must
acknowledge all correctly received bytes except the last
byte. The final byte must be followed by a not acknowl-
edge from the master and then a STOP condition. Figure
37 illustrates the frame format for reading one byte from
the IC. Figure 38 illustrates the frame format for reading
multiple bytes from the IC.
ACKNOWLEDGE FROM MAX9888
SLAVE ADDRESS
SLAVE ADDRESS
R/W
R/W
AUTOINCREMENT INTERNAL REGISTER ADDRESS POINTER
1
AUTOINCREMENT INTERNAL REGISTER ADDRESS POINTER
1
A
A
NOT ACKNOWLEDGE FROM MASTER
DATA BYTE
1 BYTE
DATA BYTE
1 BYTE
A
P
A