MAX9888EWY+T Maxim Integrated Products, MAX9888EWY+T Datasheet - Page 105

• Manufacturer Part Number: MAX9888EWY+T
• Description: IC CODEC AUDIO FLEXSOUND 63WLP
• Manufacturer: Maxim Integrated Products
• Series: DirectDrive®, FLEXSOUND™r
• Type: Class Dr

Specifications of MAX9888EWY+T

• Output Type: 3-Channel with Stereo Headphones
• Max Output Power X Channels @ Load: 1.37W x 2 @ 8 Ohm; 40mW x 2 @ 16 Ohm
• Voltage - Supply: 2.8 V ~ 5.5 V
• Features: Depop, Differential Inputs, I²S, Microphone, Mute, Shutdown
• Mounting Type: Surface Mount
• Package / Case: 63-WLP
• For Use With: MAX9888EVKIT+ - KIT EVALUATION FOR MAX9888
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The slave address is defined as the seven most signifi-
cant bits (MSBs) followed by the read/write bit. For the
IC, the seven most significant bits are 0010000. Setting
the read/write bit to 1 (slave address = 0x21) configures
the IC for read mode. Setting the read/write bit to 0 (slave
address = 0x20) configures the IC for write mode. The
address is the first byte of information sent to the IC after
the START condition.
The acknowledge bit (ACK) is a clocked 9th bit that the
IC uses to handshake receipt each byte of data when
in write mode (Figure 34). The IC pulls down SDA dur-
ing the entire master-generated 9th clock pulse if the
previous byte is successfully received. Monitoring ACK
allows for detection of unsuccessful data transfers. An
unsuccessful data transfer occurs if a receiving device
Figure 36. Writing n-Bytes of Data to the IC
Figure 34. Acknowledge
Figure 35. Writing One Byte of Data to the IC
S
S
ACKNOWLEDGE FROM MAX9888
SLAVE ADDRESS
ACKNOWLEDGE FROM MAX9888
SLAVE ADDRESS
R/W
O
SCL
SDA
A
R/W
CONDITION
START
ACKNOWLEDGE FROM MAX9888
O
REGISTER ADDRESS
A
Slave Address
Acknowledge
with FLEXSOUND Technology
1
ACKNOWLEDGE FROM MAX9888
REGISTER ADDRESS
2
A
ACKNOWLEDGE FROM MAX9888
B7 B6 B5 B4 B3 B2 B1 B0
AUTOINCREMENT INTERNAL REGISTER ADDRESS POINTER
is busy or if a system fault has occurred. In the event
of an unsuccessful data transfer, the bus master retries
communication. The master pulls down SDA during the
9th clock cycle to acknowledge receipt of data when
the IC is in read mode. An acknowledge is sent by the
master after each read byte to allow data transfer to
continue. A not acknowledge is sent when the master
reads the final byte of data from the IC, followed by a
STOP condition.
A write to the IC includes transmission of a START condi-
tion, the slave address with the R/W bit set to 0, one byte
of data to configure the internal register address pointer,
one or more bytes of data, and a STOP condition. Figure
35 illustrates the proper frame format for writing one byte
of data to the IC. Figure 35 illustrates the frame format for
writing n-bytes of data to the IC.
NOT ACKNOWLEDGE
DATA BYTE 1
ACKNOWLEDGE
1 BYTE
Stereo Audio CODEC
8
ACKNOWLEDGMENT
CLOCK PULSE FOR
A
9
B7
A
AUTOINCREMENT INTERNAL REGISTER ADDRESS POINTER
B6
ACKNOWLEDGE FROM MAX9888
B5
ACKNOWLEDGE FROM MAX9888
B7 B6 B5 B4 B3 B2 B1 B0
DATA BYTE
B4
1 BYTE
DATA BYTE n
B3
1 BYTE
B2
Write Data Format
B1
B0
A
A
P
P
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