MAX9888EWY+T Maxim Integrated Products, MAX9888EWY+T Datasheet - Page 104

• Manufacturer Part Number: MAX9888EWY+T
• Description: IC CODEC AUDIO FLEXSOUND 63WLP
• Manufacturer: Maxim Integrated Products
• Series: DirectDrive®, FLEXSOUND™r
• Type: Class Dr

Specifications of MAX9888EWY+T

• Output Type: 3-Channel with Stereo Headphones
• Max Output Power X Channels @ Load: 1.37W x 2 @ 8 Ohm; 40mW x 2 @ 16 Ohm
• Voltage - Supply: 2.8 V ~ 5.5 V
• Features: Depop, Differential Inputs, I²S, Microphone, Mute, Shutdown
• Mounting Type: Surface Mount
• Package / Case: 63-WLP
• For Use With: MAX9888EVKIT+ - KIT EVALUATION FOR MAX9888
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 38. Device Revision Register
Stereo Audio CODEC
with FLEXSOUND Technology
Device Revision
The IC features an I
serial interface comprising a serial-data line (SDA) and
a serial-clock line (SCL). SDA and SCL facilitate com-
munication between the IC and the master at clock rates
up to 400kHz. Figure 5 shows the 2-wire interface timing
diagram. The master generates SCL and initiates data
transfer on the bus. The master device writes data to the
IC by transmitting the proper slave address followed by
the register address and then the data word. Each trans-
mit sequence is framed by a START (S) or REPEATED
START (Sr) condition and a STOP (P) condition. Each
word transmitted to the IC is 8 bits long and is followed
by an acknowledge clock pulse. A master reading data
from the IC transmits the proper slave address followed
by a series of nine SCL pulses. The IC transmits data on
SDA in sync with the master-generated SCL pulses. The
master acknowledges receipt of each byte of data. Each
read sequence is framed by a START or REPEATED
START condition, a not acknowledge, and a STOP condi-
tion. SDA operates as both an input and an open-drain
output. A pullup resistor, typically greater than 500I,
is required on SDA. SCL operates only as an input. A
pullup resistor, typically greater than 500I, is required
on SCL if there are multiple masters on the bus, or if
the single master has an open-drain SCL output. Series
resistors in line with SDA and SCL are optional. Series
SMBus is a trademark of Intel Corp.
104
Figure 33. START, STOP, and REPEATED START Conditions
(Read Only)
REGISTER
0xFF
BIT
7
6
5
4
3
2
1
0
2
C/SMBusK-compatible, 2-wire
NAME
REV
SCL
SDA
I
2
C Serial Interface
Device Revision Code
REV is always set to 0x43.
S
Sr
resistors protect the digital inputs of the IC from high
voltage spikes on the bus lines, and minimize crosstalk
and undershoot of the bus signals.
One data bit is transferred during each SCL cycle. The
data on SDA must remain stable during the high period of
the SCL pulse. Changes in SDA while SCL is high are con-
trol signals (see the START and STOP Conditions section).
SDA and SCL idle high when the bus is not in use. A
master initiates communication by issuing a START
condition. A START condition is a high-to-low transition
on SDA with SCL high. A STOP condition is a low-to-
high transition on SDA while SCL is high (Figure 33). A
START condition from the master signals the beginning
of a transmission to the IC. The master terminates trans-
mission, and frees the bus, by issuing a STOP condition.
The bus remains active if a REPEATED START condition
is generated instead of a STOP condition.
The IC recognizes a STOP condition at any point during
data transmission except if the STOP condition occurs in
the same high pulse as a START condition. For proper
operation, do not send a STOP condition during the
same SCL high pulse as the START condition.
DESCRIPTION
P
START and STOP Conditions
Early STOP Conditions
Bit Transfer