TMPR4938XBG-333 TOSHIBA Semiconductor CORPORATION, TMPR4938XBG-333 Datasheet
TMPR4938XBG-333
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TMPR4938XBG-333 Summary of contents
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TX System RISC TX49 Family TMPR4938 Rev. 2.0 ...
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R4000/R4400/R5000 are a trademark of MIPS Technologies, Inc. The information contained herein is subject to change without notice. The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA ...
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Thank you for new or continued patronage of TOSHIBA semiconductor products. This is the 2005 edition of the user’s manual for the TMPR4938 64-bit RISC microprocessor. This databook is written accessible to engineers who may be ...
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Handling Precautions TMPR4938 1. Overview and Features ........................................................................................................................................... 1-1 1.1 Overview........................................................................................................................................................ 1-1 1.2 Features .......................................................................................................................................................... 1-1 1.2.1 Features of the TX49/H3 core.............................................................................................................. 1-2 1.2.2 Features of TX4938 peripheral functions ............................................................................................ 1-2 2. Configuration.......................................................................................................................................................... 2-1 2.1 TX4938 block diagram .................................................................................................................................. 2-1 ...
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Jump Address Register (JMPADR) 0xE058 ...................................................................................... 5-16 6. Clocks ............................................................................................................................................................. 6-1 6.1 TX4938 Clock Signals ................................................................................................................................... 6-1 6.2 Power-Down Mode ........................................................................................................................................ 6-5 6.2.1 Halt Mode and Doze Mode.................................................................................................................. 6-5 6.2.2 Power Reduction for Peripheral Modules............................................................................................ 6-5 6.3 Power-On Sequence ...
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Restrictions in Access to PCI Bus...................................................................................................... 8-22 8.4 DMA Controller Registers ........................................................................................................................... 8-23 8.4.1 DMA Master Control Register (DM0MCR, DM1MCR)................................................................... 8-25 8.4.2 DMA Channel Control Register (DM0CCRn, DM1CCRn) .............................................................. 8-27 8.4.3 DMA Channel Status Register (DM0CSRn, DM1CSRn)) ................................................................ 8-31 ...
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Burst Write (64-bit Bus, Slow Write Burst) ....................................................................................... 9-32 9.5.6 Single Read (32-bit Bus).................................................................................................................... 9-33 9.5.7 Single Write (32-bit Bus) ................................................................................................................... 9-35 9.5.8 Low Power Consumption and Power Down Mode ........................................................................... 9-37 9.6 SDRAM Usage Example ............................................................................................................................. 9-42 10. ...
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PCI Bus Arbiter Current Request Register (PBACREQ) 10.4.29 PCI Bus Arbiter Current Grant Register (PBACGNT) 10.4.30 PCI Bus Arbiter Current State Register (PBACSTATE) 10.4.31 G2P Memory Space 0 G-Bus Base Address Register (G2PM0GBASE) 10.4.32 G2P Memory Space 1 G-Bus ...
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Line Control Register 0 (SILCR0) 0xF300 (Ch. 0) Line Control Register 1 (SILCR1) 0xF400 (Ch. 1) ..........................................................................11-13 11.4.2 DMA/Interrupt Control Register 0 (SIDICR0) 0xF304 (Ch. 0) DMA/Interrupt Control Register 1 (SIDICR1) 0xF404 (Ch. 1)........................................................11-15 11.4.3 DMA/Interrupt Status Register 0 ...
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Configuration ............................................................................................................................................... 14-2 14.3 Functional Description................................................................................................................................. 14-3 14.3.1 CODEC Connection .......................................................................................................................... 14-3 14.3.2 Boot Configuration ............................................................................................................................ 14-4 14.3.3 Usage Flow ........................................................................................................................................ 14-5 14.3.4 AC-link Start Up................................................................................................................................ 14-7 14.3.5 CODEC Register Access ................................................................................................................... 14-8 14.3.6 Sample-data Transmission and Reception ......................................................................................... ...
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Interrupt Pending Register (IRPND) 0xF680 .................................................................................. 15-34 15.4.15 Interrupt Current Status Register (IRCS) 0xF6A0........................................................................... 15-37 15.4.16 Interrupt Request Flag Register 0 (IRFLAG0) 0xF510 ................................................................... 15-39 15.4.17 Interrupt Request Flag Register 1 (IRFLAG1) 0xF514 ................................................................... 15-40 15.4.18 Interrupt Request Polarity ...
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NAND Flash Memory IPL Control Information...............................................................................18-11 18.3.5 Data configuration of NAND Flash Memory .................................................................................. 18-17 18.3.6 NAND Flash Memory IPL Error Handling ..................................................................................... 18-26 19. On-Chip SRAM .................................................................................................................................................... 19-1 19.1 Characteristics.............................................................................................................................................. 19-1 19.2 Block diagram.............................................................................................................................................. 19-1 19.3 Detailed explanation ...
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PCI EEPROM Interface AC characteristics......................................................................................22-11 22.5.8 DMA Interface AC characteristics ....................................................................................................22-11 22.5.9 Interrupt Interface AC characteristics .............................................................................................. 22-12 22.5.10 SIO Interface AC characteristics...................................................................................................... 22-13 22.5.11 Timer Interface AC characteristics .................................................................................................. 22-13 22.5.12 PIO Interface AC characteristics...................................................................................................... 22-14 22.5.13 AC-link ...
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Handling Precautions ...
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Using Toshiba Semiconductors Safely TOSHIBA are continually working to improve the quality and the reliability of their products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It ...
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Using Toshiba Semiconductors Safely 1-2 ...
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Safety Precautions This section lists important precautions which users of semiconductor devices (and anyone else) should observe in order to avoid injury and damage to property, and to ensure safe and correct use of devices. Please be sure that ...
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General Precautions regarding Semiconductor Devices Do not use devices under conditions exceeding their absolute maximum ratings (e.g. current, voltage, power dissipation or temperature). This may cause the device to break down, degrade its performance, or cause it to catch ...
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Precautions Specific to Each Product Group 2.2.1 Optical semiconductor devices When a visible semiconductor laser is operating, do not look directly into the laser beam or look through the optical system. This is highly likely to impair vision, and ...
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Do not use devices under conditions which exceed their absolute maximum ratings (current, voltage, power dissipation, temperature etc.). This may cause the device to break down, causing a large short-circuit current to flow, which may in turn cause it to ...
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General Safety Precautions and Usage Considerations This section is designed to help you gain a better understanding of semiconductor devices ensure the safety, quality and reliability of the devices which you incorporate into your designs. 3.1 ...
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Make sure that sections of the tape carrier which come into contact with installation devices or other electrical machinery are made of a low-resistance material. (f) Make sure that jigs and tools used in the assembly process do not ...
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When storing printed circuit boards which have devices mounted on them, use a board container or bag that is protected against static charge. To avoid the occurrence of static charge or discharge due to friction, keep the boards separate ...
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Storage 3.2.1 General storage • Avoid storage locations where devices will be exposed to moisture or direct sunlight. • Follow the instructions printed on the device cartons regarding transportation and storage. • The storage area temperature should be kept ...
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General Safety Precautions and Usage Considerations • If the 12-month storage period has expired the 30% humidity indicator shown in Figure 1 is pink when the packing is opened, it may be advisable, depending on the device ...
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Design Care must be exercised in the design of electronic equipment to achieve the desired reliability important not only to adhere to specifications concerning absolute maximum ratings and recommended operating conditions also important to consider ...
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CMOS logic IC inputs, for example, have extremely high impedance input pin is left open, it can easily pick up extraneous noise and become unstable. In this case, if the input voltage level reaches an intermediate level, it ...
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Thermal design The failure rate of semiconductor devices is greatly increased as operating temperatures increase. As shown in Figure 2, the internal thermal stress on a device is the sum of the ambient temperature and the temperature rise due ...
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Decoupling Spike currents generated during switching can cause Vcc (Vdd) and GND (Vss) voltage levels to fluctuate, causing ringing in the output waveform or a delay in response speed. (The power supply and GND wiring impedance is normally 50 ...
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Peripheral circuits In most cases semiconductor devices are used with peripheral circuits and components. The input and output signal voltages and currents in these circuits must be chosen to match the semiconductor device’s specifications. The following factors must be ...
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Inspection Sequence Do not insert devices in the wrong orientation. Make sure that the positive and negative electrodes of the power supply are correctly connected. Otherwise, the rated maximum current or maximum power dissipation may be exceeded and the ...
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If lead insertion hole intervals on the printed circuit board do not precisely match the lead pitch of the device, do not attempt to forcibly insert devices by pressing on them or by pulling on their leads. (3) For ...
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Soldering temperature profile The soldering temperature and heating time vary from device to device. Therefore, when specifying the mounting conditions, refer to the individual datasheets and databooks for the devices used. (1) Using medium infrared ray reflow • Heating ...
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Do not rub device markings with a brush or with your hand during cleaning or while the devices are still wet from the cleaning agent. Doing so can rub off the markings. (4) The dip cleaning, shower cleaning and ...
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Mounting chips Devices delivered in chip form tend to degrade or break under external forces much more easily than plastic- packaged devices. Therefore, caution is required when handling this type of device. (1) Mount devices in a properly prepared ...
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Tightening torque (1) Make sure the screws are tightened with fastening torques not exceeding the torque values stipulated in individual datasheets and databooks for the devices used. (2) Do not allow a power screwdriver (electrical or air-driven) to touch ...
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Strong electrical and magnetic fields Devices exposed to strong magnetic fields can undergo a polarization phenomenon in their plastic material, or within the chip, which gives rise to abnormal symptoms such as impedance changes or increased leakage current. Failures ...
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General Safety Precautions and Usage Considerations 3-18 ...
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Precautions and Usage Considerations This section describes matters specific to each product group which need to be taken into consideration when using devices. If the same item is described in Sections 3 and 4, the description in Section 4 ...
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Precautions and Usage Considerations 4-2 ...
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TMPR4938 2005-3 Rev 2.0 ...
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Conventions in this Manual Value Conventions • Hexadecimal values are expressed as in the following example. (This value is expressed the decimal system.) • KB (kilobyte) = 1,024 Bytes, MB (megabyte) = 1,024 × 1,024 = 1,048,576 ...
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Handling reserved regions Operation is undefined when a register defined in this document as a reserved region (Reserved) is accessed. If there is a bit or field that was defined as Reserved in a register, write the expressed default value ...
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... TX4938 realizes low memory access latency and high memory bandwidth. This allows the TX4938 to show its capacity as a high-performance CPU core. 1.2 Features • TX49/H3 core Maximum Operating Frequency: 300 MHz (TMPR4938XBG-300), 333 MHz (TMPR4938XBG-333) On-chip IEEE754-compliant single/double precision floating point unit (FPU) function • External Bus Controller (8 channels) • Supports the ISA/ATA interface • ...
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Low Power Consumption Supports internal 1 block 3.3 V operation, and low power consumption mode (Halt) • Supports IEEE1149.1 (JTAG): Debugging Support Unit (EJTAG) • Package: 484-pin PBGA (with 64pin thermal ball) 1.2.1 Features of the TX49/H3 ...
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Direct Memory Access Controllers (DMAC) The TX4938 has two DMA Controllers for invoking DMA transfer with memory and I/O devices. Each DMA Controller has 4 built-in DMA Channels. • Can set internal/external DMA requests • Supports as internal DMA ...
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Serial I/O port (SIO) The TX4938 has an on-chip 2-channel asynchronous serial I/O interface (full duplex UART) • Full duplex UART × 2 channels • On-chip baud rate generator • FIFO Transmission: on-chip 8-bit × 8-stage FIFO Reception: on-chip ...
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Can select either the Edge or Level interrupt detection mode for each external interrupt • Has a built-in 16-bit read/write register as a flag register for interrupt requests. Can request interrupts to an external device or to the TX49/H3 ...
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Chapter 1 Overview and Features 1-6 ...
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Configuration 2.1 TX4938 block diagram Figure 2.1 internal block diagram of the TX4938. TX49/H3 Core FPU HALTDOZE TEST[4:0]* TEST BYPASSPLL* PLL CGRESET* CG MASTERCLK PCIAD[31:0] C_BE[3:0] PAR FRAME* IRDY* TRDY* STOP* ID_SEL DEVSEL* PCIC REQ[3:0]* GNT[3:0]* PERR* ...
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The TX4938 has the following blocks. (1) TX49/H3 Core: Consists of a CPU, System Control Coprocessor (CP0), Instruction cache, Data cache, Floating-point Unit (FPU), write buffer (WBU), Debugging Support Unit (DSU), and a G-Bus I/F. • FPU: An IEEE754-compliant single-precision ...
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Signals 3.1 Pin Signal Description In the following tables, asterisks at the end of signal names indicate active-low signals. In the Type column, PU indicates that the pin is equipped with an internal pull-up resister and PD indicates that ...
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SDRAM Interface Signals Table 3.1.2 SDRAM Interface Signals Signal Name Type SDCLK[3:0] Output SDRAM Controller Clock Clock signals used by SDRAM. The clock frequency is the same as the G-Bus clock (GBUSCLK) frequency. When these clock signals are not ...
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External Interface Signals Table 3.1.3 External Interface Signals Signal Name Type SYSCLK Output System Clock Clock for external I/O devices. Outputs a clock in full speed mode (at the same frequency as the G-Bus clock (GBUSCLK) frequency), half speed ...
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DMA Interface Signals Signal Name Type DMAREQ[3:0] Input DMA Request PU DMA transfer request signals from an external I/O device. The DMAREQ[3:1] signal shares the pin with the other function signal (refer to Section “3.3 Pin multiplex”). DMAACK[3:0] Output ...
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Table 3.1.5 PCI Interface Signals (2/2) Signal Name Type REQ[3:2]* Input Request Signals used by the master to request bus mastership. The boot configuration signal on the DATA[2] pin determines whether the built-in PCI bus arbiter is used. In internal ...
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Serial I/O Interface Signals Table 3.1.6 Serial I/O Interface Signals Signal Name Type CTS [1:0]* Input SIO Clear to Send PU CTS* signals. CTS[1]* share pins with other function signals (refer to Section “3.3 Pin multiplex”). RTS [1:0]* Output ...
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AC-link Interface Signals Signal Name Type ACRESET* Output AC '97 Master H/W Reset ACRESET* share pins with other function signals (refer to Section “3.3 Pin multiplex”). SYNC Output 48 kHz Fixed Rate Sample Sync SYNC share pins with other ...
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ISA/ATA Interface Signals Signal Name Type IOR* Output IO read PU This is IO read signal. This signal is common with the other functions (refer to Section “3.3 Pin multiplex”). Use the configuration setting during boot-up. IOW* Output IO ...
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ETHER Interface Signals (Channel 1) Table 3.1.14 ETHER Interface Signals (Channel 1) Signal Name Type E1COL Input Collision detection signal This is collision detection signal. This signal is common with the other functions (refer to Section “3.3 Pin multiplex”). ...
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NAND Flash Memory Interface Signals Table 3.1.15 NAND Flash Memory Interface Signals Signal Name Type ND_ALE Output NAND Flash Address Latch Enable PU ALE signal for NAND flash memory. These signals are common with the other functions (refer to ...
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Table 3.1.16 Extended EJTAG Interface Signals (2/2) Signal Name Type DCLK Output Debug Clock Clock output signal for the real-time debugging system. When PC trace mode is selected, the TPC[3:1] and PCST signals are output synchronously. This clock is the ...
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Power Supply Pins Signal Name Type ⎯ PLL1VDD_A, PLL Power Pins PLL2VDD_A PLL analog power supply pins. PLL1VDD_A = 1.5 V. PLL2VDD_A = 1.5 V. ⎯ PLL1VSS_A, PLL Ground Pins PLL2VSS_A PLL analog ground pins. PLL1VSS_A = 0 V. ...
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Boot Configuration The ADDR[19:0] and DATA[15:0] signals can also function as configuration signals for initially setting various functions upon booting the system. The states of the configuration signals immediately after the RESET* or CGRESET* signal is deasserted are read ...
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Table 3.2.2 Boot Configuration Specified with the ADDR[19:0] Signals (1/2) Signal Description ADDR[19] PCI Controller Mode Select Specifies the operating mode of the TX4938 PCI controller Satellite H = Host ADDR[18] Select Shared I/O Pins Specifies the function ...
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Table 3.2.2 Boot Configuration Specified with the ADDR[19:0] Signals (2/2) Signal Description ADDR[5] Select SDRAM device Select initial setting derivability of SDRAM interface signals L = 8mA H = 16mA ADDR[19:0], CKE, RAS*, CAS*, WE*, SDCS[3:0], SDCLK[3:0], SDCLKIN ADDR[4] Initial ...
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Table 3.2.3 Boot Configuration Specified with the DATA[22:0] Signals Signal Description DATA[22:16] Reserved DATA[15:8] Boot Configuration Reads the board information and accordingly sets the boot configuration field (BCFG) of the chip configuration register (CCFG). DATA[7] TX49/H3 Internal Timer Interrupt Disable ...
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Pin multiplex The TX4938 has some multiplexed pins. Each pin is used for different functions depending on the settings of the PCFG[61:58] control register and ADDR[18]/[9], DATA[6]/[3] boot configuration signal. Table 3.3.1 shows how to set the function for ...
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Signal, PCFG ECC PIO[15:8] PIO[1] PIO[0] INT[5] INT[4] INT[3] INT[2] INT[1] INT[0] CTS[1]* RTS[1]* RXD[1] TXD[1] CTS[0]* RTS[0]* Function of RXD[0] Each signal (Note3) TXD[0] (Note4) SDIN[1] DCLK PCST[8] PCST[7] PCST[6] PCST[5] PCST[4] PCST[3] PCST[2] PCST[1] PCST[0] TPC[3] TPC[2] TPC[1] ...
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Address Mapping This chapter explains the physical address map of TX4938. Please refer to "64-bit TX System RISC TX49/H2, TX49/H3, TX49/H4 Core Architecture" about the details of mapping to a physical address from the virtual address of TX49/H3 core. ...
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Register Map 4.2.1 Addressing TX4938 internal registers are to be accessed through 64 K bytes address space that is based on physical address 0xF_FF1F_0000 or pointed address by RAMP register (refer to 5.2.7). Figure 4.2.1 shows how to generate ...
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Register Map Please refer to “10.5 PCI Configuration Space Register” about PCI configuration register. Offset Address 0x0000 to 0x4FFF 0x5000 to 0x5FFF 0x6000 to 0x67FF 0x6800 to 0x6FFF 0x7000 to 0x7FFF 0x8000 to 0x8FFF 0x9000 to 0x9FFF 0xA000 to ...
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Offset Address Register Size (bit) Register Symbol NAND Flash Memory Controller (NDFMC) 0x5000 64 0x5008 64 0x5010 64 0x5018 64 0x5020 64 0x5028 64 0x5030 64 SRAM Controller (SRAMC) 0x6000 64 Chapter 4 Address Mapping Table 4.2.3 Internal Registers (1/12) ...
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Offset Address Register Size (bit) Register Symbol PCI Controller for ETHERC (PCIC1) 0x7000 32 0x7004 32 0x7008 32 0x700C 32 0x7010 32 0x7014 32 0x7018 32 0x701C 32 0x7020 32 0x7024 32 0x702C 32 0x7034 32 0x703C 32 0x7040 32 ...
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Offset Address Register Size (bit) Register Symbol PCI Controller for ETHERC (PCIC1) 0x7120 64 0x7128 64 0x7130 64 0x7138 64 0x7140 32 0x7144 32 0x7148 32 0x714C 32 0x7150 64 0x7158 64 0x7160 64 0x7168 64 0x7170 32 0x7174 32 ...
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Offset Address Register Size (bit) Register Symbol SDRAM Controller (SDRAMC) 0x8000 64 0x8008 64 0x8010 64 0x8018 64 0x8040 64 0x8058 64 External Bus Controller (EBUSC) 0x9000 64 0x9008 64 0x9010 64 0x9018 64 0x9020 64 0x9028 64 0x9030 64 ...
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Offset Address Register Size (bit) Register Symbol DMA Controller (DMAC0) 0xB000 64 0xB008 64 0xB010 64 0xB018 64 0xB020 64 0xB028 64 0xB030 64 0xB038 64 0xB040 64 0xB048 64 0xB050 64 0xB058 64 0xB060 64 0xB068 64 0xB070 64 ...
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Offset Address Register Size (bit) Register Symbol DMA Controller (DMAC1) 0xB800 64 0xB808 64 0xB810 64 0xB818 64 0xB820 64 0xB828 64 0xB830 64 0xB838 64 0xB840 64 0xB848 64 0xB850 64 0xB858 64 0xB860 64 0xB868 64 0xB870 64 ...
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Offset Address Register Size (bit) Register Symbol PCI Controller (PCIC) 0xD000 32 0xD004 32 0xD008 32 0xD00C 32 0xD010 32 0xD014 32 0xD018 32 0xD01C 32 0xD020 32 0xD024 32 0xD02C 32 0xD034 32 0xD03C 32 0xD040 32 0xD080 32 ...
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Table 4.2.3 Internal Registers (8/12) Offset Address Register Size (bit) Register Symbol 0xD120 64 0xD128 64 0xD130 64 0xD138 64 0xD140 32 0xD144 32 0xD148 32 0xD14C 32 0xD150 64 0xD158 64 0xD160 64 0xD168 64 0xD170 32 0xD174 32 ...
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Offset Address Register Size (bit) Register Symbol Configuration 0xE000 64 0xE008 64 0xE010 64 0xE018 64 0xE020 64 0xE030 64 0xE048 64 0xE050 64 Timer (Channel 0) 0xF000 32 0xF004 32 0xF008 32 0xF00C 32 0xF010 32 0xF020 32 0xF030 ...
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Table 4.2.3 Internal Registers (10/12) Offset Address Register Size (bit) Register Symbol Serial I/O (Channel 0) 0xF300 32 0xF304 32 0xF308 32 0xF30C 32 0xF310 32 0xF314 32 0xF318 32 0xF31C 32 0xF320 32 Serial I/O (Channel 1) 0xF400 32 ...
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Table 4.2.3 Internal Registers (11/12) Offset Address Register Size (bit) Register Symbol Interrupt Controller (IRC) 0xF510 32 0xF514 32 0xF518 32 0xF51C 32 0xF520 32 0xF524 32 0xF600 32 0xF604 32 0xF608 32 0xF610 32 0xF614 32 0xF618 32 0xF61C ...
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Table 4.2.3 Internal Registers (12/12) Offset Address Register Size (bit) Register Symbol AC-link Controller (ACLC) 0xF700 32 0xF704 32 0xF708 32 0xF710 32 0xF714 32 0xF718 32 0xF71C 32 0xF720 32 0xF740 32 0xF744 32 0xF748 32 0xF74C 32 0xF750 ...
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Chapter 4 Address Mapping 4-16 ...
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Configuration Registers 5.1 Detailed Description The configuration registers set up and control the basic functionality of the entire TX4938. Refer to Section 5.2 for details of each configuration register. Also refer to sections mentioned in the description about each ...
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Registers Table 5.2.1 lists the configuration registers. Table 5.2.1 Configuration Register Mapping Offset Address Size in Bits 0xE000 64 0xE008 64 0xE010 64 0xE018 64 0xE020 64 0xE030 64 0xE048 64 0xE058 64 Any address not defined in this ...
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Chip Configuration Register (CCFG) For the bit fields whose initial values are set by boot configuration (refer to Section 3.2), the initial input signal level and the corresponding register value are indicated Reserved ...
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Bit Mnemonic Field Name PCI 66MHz Used to inform the device connected to the PCI bus that PCI66 Mode MHz operation performed. This bit is valid only when the PCI controller of the TX4938 ...
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Bit Mnemonic Field Name 12:10 PCIDIVMODE PCICLK Specifies the frequency division ratio of the PCI bus clock Frequency output (PCICLK[5:0]) frequency to the clock frequency Division Ratio (CPUCLK) of the TX49/H3 core. 001: PCICLK frequency = CPUCLK frequency ÷ 4 ...
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Chip Revision ID Register (REVID MJERREV MINEREV R 0x0 0x0 Bit Mnemonic Field Name ⎯ 63:32 Reserved 31:16 PCODE Product Code Indicates the product number fixed value. 15:12 MJERREV Major ...
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Pin Configuration Register (PCFG) For the bit fields whose initial values are set by boot configuration (refer to Section 3.2), the initial input signal level and the corresponding register value are indicated ATA_SEL ...
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Bit Mnemonic Field Name DATA Signal 56 DRVDATA Specifies the driving capability of the DATA[63:0] signals. Control Signal 55 DRVCB Specifies the driving capability of the CB[7:0]* ...
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Bit Mnemonic Field Name 26:23 SDCLKEN [3:0] SDCLK Enable Individually specifies whether to output each of SDCLK[3:0 Clock output Bit 26 = SDCLK[3] Bit 25 = SDCLK[2] Bit 24 = SDCLK[1] Bit 23 = SDCLK[0] ...
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Timeout Error Access Address Register (TOEA Reserved 31 15 Bit Mnemonic Field Name ⎯ 63:36 Reserved Timeout Error Holds the G-Bus address for the G-Bus cycle in which the 35:0 TOEA Access latest G-Bus timeout error was ...
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Clock Control Register (CLKCTR) Bit 32 and bits 15-0 are reset bits for the on-chip peripheral modules. To bring on-chip peripheral modules out of the reset state, the corresponding bits must be cleared by software. Before clearing them, wait ...
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Bit Mnemonic Field Name ACLC Clock 25 ACLCKD Controls clock pulses for the AC-link controller. Disable 0 = Supply clock pulses not supply clock pulses. PIO Clock 24 PIOCKD Controls clock pulses for the parallel IO controller. ...
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Bit Mnemonic Field Name 7 DMARST DMAC Reset Resets the DMA controller Normal state 1 = Reset 6 PCICRST PCIC Reset Resets the PCI controller Normal state 1 = Reset ⎯ ⎯ 5 Always set this ...
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G-Bus Arbiter Control Register (GARBC ARBMD R Reserved Bit Mnemonic Field Name ⎯ 63:32 Reserved Arbitration 31 ARBMD Specifies how to prioritize G-Bus arbitration. Mode 0 = Fixed priority. The G-Bus arbitration ...
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Register Address Mapping Register (RAMP Reserved 15 Bit Mnemonic Field Name ⎯ 63:20 Reserved Register This is a base address register for the TX4938 built-in 19:0 RAMP[35:16] Address registers. It holds the high-order 20 bits of ...
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Jump Address Register (JMPADR Bit Mnemonic Field Name JMPADR[63:0] Jump Address When NAND-IPL loads a user boot program to RAM from a 63:0 Register NAND flash memory, the address of the loading place is set ...
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Clocks 6.1 TX4938 Clock Signals Figure 6.1.1 shows the configuration of TX4938 blocks and clock signals. Table 6.1.1 describes each clock signal. Table 6.1.2 shows the relationship among different clock signals when the CPU clock frequency is 266 MHz. ...
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Table 6.1.1 TX4938 Clock Signals (1/2) Clock Input/Output MASTERCLK Input Master input clock for the TX4938. The TX4938 internal clock generator multiplies or divides MASTERCLK to generate internal clock pulses. CPUCLK Internal signal Clock supplied to the TX49/H3 core. PLL1 ...
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Table 6.1.1 TX4938 Clock Signals (2/2) Clock Input/Output PCICLK[5:0] Output Clock supplied to devices on the PCI bus. The PCICLKEN bit of the PCFG register can disable the output of PCICLK. The frequency depends on boot configuration signals ADDR[11:10] or ...
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... HHLL (×4.0) 66.5 16.6 HLLL (×16.0) 59.1 LHHH (×4.5) 59.1 14.8 LLHH (×18.0) † The CCFG.PCIDIVMODE[2:1] field is setting by the boot configuration ADDR[11:10]. Table 6.1.3 Relationship Among Different Clock Frequencies (for TMPR4938XBG-300, CPUCLK = 300 MHz) Master Clock (Input) Internal Clock and Boot Configured Settings Boot Configured MASTERCLK CPUCLK GBUSCLK ...
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... Table 6.1.4 Relationship Among Different Clock Frequencies (for TMPR4938XBG-333, CPUCLK = 333 MHz) Master Clock (Input) Internal Clock and Boot Configured Settings Boot Configured MASTERCLK CPUCLK GBUSCLK IMBUSCLK Setting (MHz) (MHz) (MHz) ADDR[3:0] - HHHH(x2. HLHH(x8.0) 133 HHHL (x2.5) 133 33 HLHL (x10.0) 111 HHLH (x3.0) 333 ...
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Power-On Sequence Vdd MASTERCLK RESET* CGRESET* PLL settling time PLL1 output CPUCLK GBUSCLK PCICLK PCICLKIN (when PCICLK is fed back) PLL2 output PCICLKO (clock for TX4938 PCI controller) Figure 6.3.1 Power-On Sequence Chapter 6 Clocks PLL settling time 6-6 ...
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External Bus Controller 7.1 Features The External Bus Controller is used for accessing ROM, SRAM memory, and I/O peripherals. The features of this bus are described below. (1) 8 independent channels (2) Supports access to ROM (mask ROM, page ...
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Block Diagram G-Bus G-Bus I/F ACEHOLD Register Address Decoder Boot Options Host I/F Timing Control EBIF CONTROL Figure 7.2.1 Block Diagram of External Bus Controller Chapter 7 External Bus Controller External Bus Controller (EBUSC) Channel Control Register CH0 Address ...
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Detailed Explanation 7.3.1 External Bus Control Register The External Bus Controller (EBUSC) has eight channels. This register contains one Channel Control Register (EBCCRn) for each channel, and all settings can be made independently for each channel. Either Word or ...
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Global/Boot-up Options In addition to the settings made separately for each channel, the Channel Control Registers can also use global options that make settings common to all channels. External Bus Controller Channel 0 can be used as a Boot ...
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Address Mapping Each of the eight channels can use the Base Address field (EBCCRn.BA[35:20]) and the Channel Size field (EBCCRn.CS[3:0]) of the External Bus Channel Control Register to map to any physical address. A channel is selected when the ...
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External Address Output The maximum memory space size for each channel (230B). Addresses are output by dividing the 20-bit ADDR[19:0] signal into two parts: the upper address and the lower address. The address bit output to ...
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Data Bus Size The External Bus Controller supports devices with a data bus width of 8 bits, 16 bits, and 32 bits. The data bus width is selected using the BSZ field of the Channel Control Register (EBCCRn). The ...
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Bus Width Mode DATA[7:0] becomes valid. Bits [19:0] of the physical address are output to ADDR[19:0]. The internal address bits [27:20], which are the upper address, are multiplexed to external ADDR[19:12]. In other words, the address is shifted ...
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Access Mode The following four modes are available as controller access modes. These modes can be set separately for each channel. • Normal mode • Page mode • External ACK mode • Ready mode Depending on the combination of ...
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Normal Mode When in this mode, the ACK*/Ready signal becomes an ACK* output when the ACK*/Ready Dynamic mode. The ACK*/Ready signal becomes High-Z when the ACK*/Ready Static mode. Wait cycles are inserted according ...
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Ready Mode When in this mode, the ACK*/Ready pin becomes Ready input, and the cycle is ended by Ready input from an external device. Ready input is internally synchronized. See Section “7.3.7.5 Ready Input Timing” for more information regarding ...
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Page Mode When in this mode, the ACK*/Ready pin becomes ACK* output when the Dynamic mode. When the ACK*/Ready Static mode, the ACK*/Ready signal becomes HiZ. Wait cycles are inserted into the access ...
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Access Timing 7.3.7.1 SHWT Option The SHWT option is selected when the SHWT (Setup/Hold Wait Time) field of the Channel Control Register is a value other than “0.” This option inserts Setup cycles and Hold cycles between signals as ...
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SYSCLK CE*/BE* ADDR [19:0] OE* SWE*/BWE* DATA [31:0] ACK*/READY (Output) Figure 7.3.6 SHWT 1 Wait (Normal Mode, Single Read/Write Cycle) 7.3.7.2 ACK*/READY Input/Output Switching Timing When in the ACK*/Ready Static mode, the ACK*/Ready signal is always an input signal. When ...
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ACK* Output Timing (Normal Mode, Page Mode) When in the Normal mode and Page mode of the ACK*/Ready Dynamic mode, the ACK* signal becomes an output signal and is asserted for one clock cycle to send notification to the ...
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ACK* Input Timing (External ACK Mode) The ACK* signal becomes an input signal when in the external ACK mode. During a Read cycle, data is latched two clock cycles after assertion of the ACK* signal is acknowledged (Figure 7.3.9 ...
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SYSCLK CE* ADDR [19:0] OE* DATA [31:0] ACK*/READY (Input) Figure 7.3.11 ACK* Input Timing (Burst Read Cycle) SYSCLK CE* ADDR [19:0] SWE*/BWE* DATA [31:0] ACK*/READY (Input) Acknowledge ACK* Figure 7.3.12 ACK* Input Timing (Burst Write Cycle) Chapter 7 External Bus ...
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Ready Input Timing The ACK*/Ready pin is used as a Ready input when in the Ready mode. The Ready input timing is the same as the ACK* input timing explained in 7.3.7.4 ACK* Input Timing (External ACK Mode) with ...
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SYSCLK CE* ADDR [19:0] SWE*/BWE* DATA [31:0] ACK*/READY (Input) SYSCLK CE* ADDR [19:0] SWE*/BWE* DATA [31:0] ACK*/READY (Input) Start Ready Check Figure 7.3.14 Ready Input Timing (Write Cycle) 7.3.8 Clock Options External devices connected to the external bus can use ...
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ISA /ATA Mode TMPR4938 supports ISA I/O space access and ATA PIO transfer mode. Since the pins used in ISA/ATA mode are multiplexed pins, select ISA/ATA before use of these pins. Since the signal of CE* is not used ...
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Usage Considerations To use ISA and ATA modules in READY, their ICCHRDY or IORDY pin should be connected to the ACK*/READY pin of the TX4938. The SHWT option allows users to adjust the setup and hold timing of IOR* ...
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ISA module Following is a programming example to use a 16-bit ISA module: • ISA mode (EBCCRn.ISA=01) • 16-bit bus (EBCCRn.BSZ=10) • READY mode (EBCCRn.RDY=1, EBCCRn.PM=00) • Channel enable (EBCCRn.ME=1) • ISA select (PCFG.ISA_SEL=1) Program the number of ...
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ATA Following is a programming example to use an ATA module: • ISA/ATA mode (EBCCRn=11) • 16-bit bus (EBCCRn=10) • READY mode (EBCCRnRDY=1, EBCCRN.PM=00) • Channel enable (EBCCRn.ME=1) • ISA/ATA pin select mode (PCFG.ISA_SEL=1, PCFG.ATA_SEL=1) Program the number of ...
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Register Table 7.4.1 External Bus Controller (EBUSC) Registers Offset Address Bit Width Register Symbol 0x9000 64 0x9008 64 0x9010 64 0x9018 64 0x9020 64 0x9028 64 0x9030 64 0x9038 64 Chapter 7 External Bus Controller Register Name EBCCR0 E-Bus ...
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External Bus Channel Control Register (EBCCRn) Channel 0 can be used as Boot memory. Therefore, the default is set by the Boot signal (see 7.3.2 Global/Boot-up Options). Channels have the same register configuration as Channel 0, ...
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Bit Mnemonic Field Name 19:18 PM Page Mode External Bus Control Page Mode Page Size (Default: 00) Page Size Specifies the Page mode (Page mode memory support) use and page size. 00: Normal mode 01: 4-page mode 10: 8-page mode ...
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Bit Mnemonic Field Name 7 BC Byte Control External Bus Byte Control (Default: DATA[5]/0) Specifies whether to use the BWE*[3:0] signal as an asserted Byte Write Enable signal (BWE*[3:0]) only during a Write cycle use ...
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Timing Diagrams 7.5 Please take the following points into account when referring to the timing diagrams. (1) The clock frequency of the SYSCLK signal can be set to one of the following divisions of the internal bus clock (GBUSCLK): 1/1, ...
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ACE* Signal Figure 7.5.1 ACE* Signal (CCFG.ACEHOLD=1, PWT: WT=0, SHWT=0, Normal) Chapter 7 External Bus Controller 7-29 ...
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Figure 7.5.2 ACE* Signal (CCFG.ACEHOLD=0, PWT: WT=0, SHWT=0, Normal) Chapter 7 External Bus Controller 7-30 ...
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Normal mode access (Single, 32-bit Bus) Figure 7.5.3 Double-word Single Write (PWT: WT=0, SHWT=0, Normal, 32-bit Bus) Chapter 7 External Bus Controller 7-31 ...
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S1 SYSCLK CE* ADDR[19:0] ACE* OE*/BUSSPRT* SWE* BWE* BE* f DATA[31:0] ACK* Figure 7.5.4 Double-word Single Read (PWT: WT=0, SHWT=0, Normal, 32-bit Bus) Chapter 7 External Bus Controller 7- ...
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Figure 7.5.5 1-word Single Write (PWT: WT=0, SHWT=0, Normal, 32-bit Bus) Chapter 7 External Bus Controller 7-33 ...
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Figure 7.5.6 1-word Single Read (PWT: WT=0, SHWT=0, Normal, 32-bit Bus) Chapter 7 External Bus Controller 7-34 ...
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Normal mode access (Burst, 32-bit Bus) Figure 7.5.7 4-word Burst Write (PWT: WT=1, SHWT=0, Normal, 32-bit Bus) Chapter 7 External Bus Controller 7-35 ...
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S1 SW1 S2 SYSCLK CE* ADDR[19:0] 0 ACE* OE*/BUSSPRT* SWE* BWE DATA[31:0] ACK* Figure 7.5.8 4-word Burst Write (PWT: WT=1, SHWT=0, Normal, 32-bit Bus) Chapter 7 External Bus Controller S1 SW1 S2 S1 SW1 ...
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Normal Mode Access (Single, 16-bit bus) Figure 7.5.9 Double-word Single Write (PWT: WT=0, SHWT=0, Normal, 16-bit Bus) Chapter 7 External Bus Controller 7-37 ...
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Figure 7.5.10 Double-word Single Read (PWT: WT=0, SHWT=0, Normal, 16-bit Bus) Chapter 7 External Bus Controller 7-38 ...
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Figure 7.5.11 Half-word Single Write (PWT: WT=0, SHWT=0, Normal, 16-bit Bus) Chapter 7 External Bus Controller 7-39 ...
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Figure 7.5.12 Half-word Single Read (PWT: WT=0, SHWT=0, Normal, 16-bit Bus) Chapter 7 External Bus Controller 7-40 ...
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Normal Mode Access (Burst, 16-bit Bus) Figure 7.5.13 4-word Burst Read (PWT: WT=0, SHWT=0, Normal, 16-bit Bus) Chapter 7 External Bus Controller 7-41 ...
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Figure 7.5.14 4-word Burst Write (PWT: WT=0, SHWT=0, Normal, 16-bit Bus) Chapter 7 External Bus Controller 7-42 ...
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Normal Mode Access (Single, 8-bit Bus) Figure 7.5.15 Double-word Single Write (PWT: WT=0, SHWT=0, Normal, 8-bit Bus) Chapter 7 External Bus Controller 7-43 ...
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Figure 7.5.16 Double-word Single Read (PWT: WT=0, SHWT=0, Normal, 8-bit Bus) Chapter 7 External Bus Controller 7-44 ...
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S1 SYSCLK CE* ADDR [19:0] ACE* OE*/BUSSPRT* SWE* BWE* f BE* f DATA [7:0] ACK* Figure 7.5.17 1-byte Single Write (PWT: WT=1, SHWT=0, Normal, 8-bit Bus) SYSCLK CE* ADDR [19:0] ACE* OE*/BUSSPRT* SWE* BWE* f BE* DATA [7:0] ACK* Figure ...
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Normal Mode Access (Burst, 8-bit Bus) Figure 7.5.19 4-word Burst Write (PWT: WT=0, SHWT=0, Normal, 8-bit Bus) Chapter 7 External Bus Controller 7-46 ...
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Figure 7.5.20 4-word Burst Read (PWT: WT=0, SHWT=0, Normal, 8-bit Bus) Chapter 7 External Bus Controller 7-47 ...
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Page Mode Access (Burst, 32-bit Bus) Figure 7.5.21 8-word Burst Write (WT=1, PWT=0, SHWT=0, 4-page, 32-bit Bus) Chapter 7 External Bus Controller 7-48 ...
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Figure 7.5.22 4-word Burst Read (WT=2, PWT=1, SHWT=0, 4-page, 32-bit Bus) Chapter 7 External Bus Controller 7-49 ...
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External ACK Mode Access (32-bit Bus) S1 SYSCLK CE* ADDR[19:0] ACE* OE*/BUSSPRT* SWE* BWE* f BE* f DATA[31:0] ACK* Note 1: The TX4938 sets the ACK* signal to High Impedance in the S1 State. Note 2: External devices drive ...
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Figure 7.5.25 4-word Burst Write (0 Wait, SHWT=0, External ACK*, 32-bit Bus) Chapter 7 External Bus Controller 7-51 ...
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Figure 7.5.26 4-word Burst Read (0 Wait, SHWT=0, External ACK*, 32-bit Bus) Chapter 7 External Bus Controller 7-52 ...
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Figure 7.5.27 Double-word Single Write (1 Wait, SHWT=2, External ACK*, 32-bit Bus) Chapter 7 External Bus Controller 7-53 ...
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Figure 7.5.28 Double-word Single Read (0 Wait, SHWT=2, External ACK*, 32-bit Bus) Chapter 7 External Bus Controller 7-54 ...
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AS1 AS2 CS1 SYSCLK CE* ADDR[19:0] ACE* OE*/BUSSPRT* SWE* BWE DATA[31:0] ACK* Figure 7.5.29 1-word Single Write (1 Wait, SHWT=2, External ACK*, 32-bit Bus) AS1 AS2 CS1 SYSCLK CE* ADDR[19:0] ACE* OE*/BUSSPRT* SWE* BWE DATA[31:0] ...
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READY Mode Access (32-bit Bus) Figure 7.5.31 1-word Single Write (PWT: WT=2, SHWT=1, READY, 32-bit Bus) Chapter 7 External Bus Controller 7-56 ...
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Figure 7.5.32 1-word Single Read (PWT: WT=2, SHWT=1, READY, 32-bit Bus) Chapter 7 External Bus Controller 7-57 ...
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ISA IO Space Access Figure 7.5.33 1-byte Write Access for the ISA IO Space (READY, SHWT=2, 8-bit Bus) Chapter 7 External Bus Controller 7-58 ...
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Figure 7.5.34 1-byte Read Access for the ISA IO Space (READY, SHWT=2, 8-bit Bus) Chapter 7 External Bus Controller 7-59 ...
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ATA/PIO Transfer Mode Access Figure 7.5.35 1-half-word Write Access for the ATA/PIO Space (CS0) (READY, SHWT=2, 16-bit Bus) Chapter 7 External Bus Controller 7-60 ...
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Figure 7.5.36 1-half-word Read Access for the ATA/PIO Space (CS1) (READY, SHWT=2, 16-bit Bus) Chapter 7 External Bus Controller 7-61 ...
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Flash ROM, SRAM Usage Example 7.6 Figure 7.6.1 illustrates example Flash ROM connections, and Figure 7.6.2 illustrates example SRAM connections. Also, Figure 7.6.3 illustrates example connections with the SDRAM and the bus separated. Since connecting multiple memory devices such as ...
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TX4938 DQM[7] DQM[7:0] ADDR[17:5] ADDR[19:0] ADDR[19] ADDR[18] SDCS*[0] RAS* CAS* WE* SDCLKIN SDCLK[0] CKE DATA[63:0] CE*[0] SWE* OE* BUSSPRT* ADDR[12] ACE* Figure 7.6.3 Connection Example with SDRAM and the Bus Separated Chapter 7 External Bus Controller SDRAM (x16 Bits) DQM[6] ...
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Chapter 7 External Bus Controller 7-64 ...
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DMA Controller 8.1 Features The TX4938 contains two four-channel DMA Controller (DMAC0, DMAC1) that executes DMA (Direct Memory Access) with memory and I/O devices. The DMA Controller has the following characteristics. <DMAC0, DMAC1> • Has four on-chip DMA channels ...
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Block Diagram DMAC0 DMA Control 0 DM0MCR Block DM0MFDR G-Bus I/F FIFO (8 Double Words) DMA Channel Arbiter Figure 8.2.1 DMA0 Controller Block Diagram Chapter 8 DMA Controller DMAREQ[0] DM0CHAR0 DMA0 DREQ0 Channel 0 DM0SAR0 DMAACK[0] DM0DAR0 DACK0 DM0CNTR0 ...
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DMAC0 DMA1 Channel 0 DMA Control 1 DM1MCR Block DM1MFDR G-Bus I/F DMA1 Channel 1 FIFO (8 Double Words) DMA1 Channel 2 DMA Channel Arbiter DMA1 Channel 3 Figure 8.2.2 DMA1 Controller Block Diagram 8-3 Chapter 8 DMA Controller DM1CHAR0 ...
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Detailed Explanation 8.3.1 Transfer Mode The DMA Controller (DMAC0, DMAC1) supports five transfer mode types (refer to Table 8.3.1 below). The setting of the External Request bit (DMCCRn.EXTRQ) of the DMA Channel Control Register selects whether transfer with an ...
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On-chip Registers The DMA Controller has two shared registers that are shared by four channels. Section 8.4 explains each register in detail. • Shared Registers DMMCR: DMA Master Control Register DMMFDR: DMA Memory Fill Data Register • DMA Channel ...
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When edge detection is set (DMCCRn.EGREQ = 1) Please set up assertion of the DMAREQ[n] signal so the DMAREQ[n] signal is asserted after the DMAACK[n] signal corresponding to a previously asserted DMAREQ[n] signal is deasserted. The DMAREQ[n] signal will ...
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Dual Address Transfer If the Single Address bit (DMCCRn.SNGAD) has been cleared, access to external I/O devices and to external memory is each performed continuously. Each access is the same as normal access except when the DMAACK[n] signal is ...
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When the Chain End bit (CHDN) is cleared, the DMADONE* signal is asserted when the DMAACK[n] signal for the last data transfer in a DMA transfer specified by the current DMA Channel Register is asserted. Namely, if the Link List ...
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Memory-Memory Copy Mode It is possible to copy memory from any particular address to any other particular address when in the Memory-Memory Copy mode. Set the DMA Channel Control Register (DMCCRn) as follows. • DMCCRn.EXTRQ = 0: Memory Transfer ...
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Channel Register Settings During Single Address Transfer Table 8.3.2 shows restrictions of the Channel Register settings during Single Address transfer. If these restrictions are not met, then a Configuration Error is detected, the Configuration Error bit (CFERR) of the ...
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Burst Transfer During Single Address Transfer According to the SDRAM Controller and External Bus Controller specifications, the DMA Controller cannot perform Burst transfer that spans across 32-double word boundaries. Consequently, if the address that starts DMA transfer is not ...
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Dual Address Transfer This section explains the register settings for Dual Address transfer (DMCCRn.SNGAD = 0). This applies to the following DMA transfer modes. • External I/O (Dual Address) transfer • Internal I/O DMA transfer • Memory-Memory Copy transfer ...
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Table 8.3.3 Channel Register Setting Restrictions During Dual Address Transfer DMSARn[2:0] Transfer Setting DMSAIRn DMSAIRn Size setting is a setting is 0 (DMCCRn.XFSZ) negative or greater value 1 Byte *** *** 2 Bytes **0 **0 4 Bytes *00 *00 8 ...
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Source Address FIFO (8 Double Words Figure 8.3.3 Dual Address Burst Transfer (DMCCRn.USEXFSZ = 1) Figure 8.3.4 shows ...
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When the Destination Burst Inhibit bit (DMCCRn.DBINH) is set, data written from the FIFO to the Destination Address is divided into multiple 8-byte Single Write transfers, then transfer is executed. When the Burst Inhibit bit is set, the TX4938 always ...
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Source Address FIFO (8 Double Words (a) Address offset is equivalent ...
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DMA Transfer The sequence of DMA transfer that uses only the DMA Channel Register is as follows below. 1. Select DMA request signal When performing external I/O or internal I/O DMA, set the DMA Request Select field (PCFG.DMASEL) of ...
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Chain DMA Transfer Table 8.3.4 shows the data structure in memory that the DMA Command Descriptor has. When the Simple Chain bit (SMPCHN) of the DMA Channel Control Register (DMCCRn) is set, only the initial four double words are ...
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Figure 8.3.5 DMA Command Descriptor Chain The sequence of Chain DMA transfer is as follows below. ...
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Initiate DMA transfer Setting the address of the DMA Command Descriptor at the beginning of the chain list in the DMA Chain Address Register (DMCHARn) automatically initiates DMA transfer. First, the value stored in each field of the DMA ...
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Interrupts An interrupt number (10 – 13) of the Interrupt Controller is mapped to each channel. In addition, there are completion interrupts for when transfer ends normally and error interrupts for when transfer ends abnormally for each channel. When ...
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Arbitration Among DMA Channels The DMA Controller has an on-chip DMA Channel Arbiter that arbitrates bus ownership among four DMA channels that use the internal bus (G-Bus). There are two methods for determining priority: the round robin method and ...
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DMA Controller Registers Table 8.4.1 DMA Controller 0 Registers Offset Address Bit Width 0xB000 64 0xB008 64 0xB010 64 0xB018 64 0xB020 64 0xB028 64 0xB030 64 0xB038 64 0xB040 64 0xB048 64 0xB050 64 0xB058 64 0xB060 64 ...
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Table 8.4.2 DMA Controller 1 Registers Offset Address Bit Width Mnemonic 0xB800 64 DM1CHAR0 0xB808 64 DM1SAR0 0xB810 64 DM1DAR0 0xB818 64 DM1CNTR0 0xB820 64 DM1SAIR0 0xB828 64 DM1DAIR0 0xB830 64 DM1CCR0 0xB838 64 DM1CSR0 0xB840 64 DM1CHAR1 0xB848 64 ...
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DMA Master Control Register (DM0MCR, DM1MCR) Offset address: DMAC0 0xB150, DMAC1 0xB950 This register controls the entire DMA Controller EIS[3:0] R 0000 FIFVC FIFWP R 000 Bit Mnemonic Field Name ...
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Bit Mnemonic Field Name FIFO Use Enable [3:0] (Default: 0x0) 6:3 FIFUM[3:0] FIFO Use Enable [3:0] Each channel specifies whether to use 8-double word FIFO in Dual Address transfer. FIFUM[n] corresponds to channel n. Refer to “8.3.8.2 Burst Transfer During ...