ST10F166BQ1 STMicroelectronics, ST10F166BQ1 Datasheet

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MCU WITH 256K FLASH MEMORY High Performance 16-bit CPU with 4-Stage Pipeline 100 ns Instruction Cycle Time at 20 MHz CPU Clock 500 ns Multiplication (16 16 bit Division ( bit) Enhanced Boolean Bit Manipulation ...

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Table of Contents ST10F166 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

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ST10F166 1 INTRODUCTION The ST10F166 is the FLASH memory members of the ST10 family of microcontrol- lers developed and produced by SGS-THOMSON Microelectronics in CMOS tech- nology. they combine high CPU performance ( million instructions per sec- ond) ...

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Figure 2. Pin Configuration Rectangular PQFP-100 (top view ST10F160 / ST10F166 EBC1 PP ST10F166 VR02056 4/62 ...

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ST10F166 Table 1. Pin Definition and Function Pin Input (I) Symbol Number Output ( I/O P4.0 – P4 XTAL1 20 I XTAL2 BUSACT, EBC1, 23 EBC0 ...

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Table 1. Pin Definition and Function Pin Input (I) Symbol Number Output ( NMI ALE P1.0 – I/O P1. P5.0 – 48 – P5.9 56 ...

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ST10F166 Table 1. Pin Definition and Function Pin Input (I) Symbol Number Output (O) 80 – 92, I/O 95 – P3.0 – P3. ...

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MEMORY ORGANIZATION The memory space of the ST10F166 is configured in a Von Neumann architecture which means that code memory, data memory, registers and I/O ports are organized within the same linear address space which currently includes 256 Kbytes. ...

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ST10F166 3 EXTERNAL BUS CONTROLLER All external memory accesses are performed by the on-chip External Bus Controller (EBC). During Reset, it can be programmed to either the Single Chip Mode when no external memory is required one of ...

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Figure 3. Memory Organization ST10F166 10/62 ...

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ST10F166 4 FLASH MEMORY The ST10F166 provides, in addition to the RAM bytes of Electrically Erasable and reprogram-mable non-volatile (FLASH) memory. This memory is organised bit allowing a complete instruction to be read during ...

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FLASH MEMORY PROGRAMMING AND ERASURE The FLASH memory is programmed using the PRESTO F Program Write algorithm for reliability. This algorithm provides a typical programming time per word and erasing of 1s per bank. Erasure of ...

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ST10F166 Figure 4. PRESTO F Program Write Algorithm PCOUNT=PNmax? PCOUNT=PCOUNT+1 13/ VR02057A ...

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Figure 5. PRESTO F Erase Algorithm PCOUNT=ENmax? PCOUNT=PCOUNT+1 ST10F166 = 0 VR02057B 14/62 ...

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ST10F166 7 CENTRAL PROCESSING UNIT (CPU) The main core of the CPU consists of a 4-stage instruction pipeline, a 16-bit arithme- tic and logic unit (ALU) and dedicated SFRs. Additional hardware provide a separate multiply and divide unit, a bit-mask ...

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C.P.U. (Cont’d) The high performance offered by the hardware implementation of the CPU can effi- ciently be used by a programmer via the highly functional ST10F166 instruction set which includes the following instruction classes: – Arithmetic Instructions – Logical Instructions ...

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ST10F166 8 INTERRUPT SYSTEM With an interrupt response time within a range from 250 ns to 500 ns (in case of inter- nal program execution), the ST10F166 is capable of reacting very fast to the occur- ance of non-deterministic events. ...

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Interrupt System (Cont’d) The following table shows all of the possible ST10F166 interrupt sources and the cor- responding hardware-related interrupt flags, vectors, vector locations and trap (inter- rupt) numbers: Table 3. Interrupt Sources and Hardware Location Source of Interrupt or ...

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ST10F166 Interrupt System (Cont’d) Except when another higher prioritized trap service being in progress, a hardware trap will interrupt any actual program execution. In turn, hardware trap services can normally not be interrupted by standard or PEC interrupts. The following ...

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A/D CONVERTER For analog signal measurement, a 10-bit A/D converter with 10 multiplexed input channels, a sample and hold circuit has been integrated on-chip. It uses the method of successive approximation which returns the conversion result for an analog ...

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ST10F166 10 SERIAL CHANNELS Serial communication with other microcontrollers, processors, terminals, or external peripheral components is provided by two serial interfaces with identical functionality, Serial Channel 0 (ASC0) and Serial Channel 1 (ASC1). They support full-duplex asynchronous communication up to ...

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WATCHDOG TIMER The Watchdog Timer of the ST10F166 represents one of the fail-safe mechanisms which have been implemented to prevent the controller from malfunctioning for longer periods of time. The Watchdog Timer of the ST10F166 is always enabled after ...

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ST10F166 13 CAPTURE/COMPARE UNIT (CAPCOM) The CAPCOM unit supports generation and control of timing sequences channels, with a maximum resolution of 400 ns. The CAPCOM unit is typically used to handle high speed I/O tasks such ...

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CAPCOM (Cont’d) Table 5. Compare Modes Compare Modes Functions Interrupt-only compare mode; Mode 0 several compare interrupts per timer period are possible Pin toggles on each compare match; Mode 1 several compare events per timer period are possible Interrupt-only compare ...

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ST10F166 14 GENERAL PURPOSE TIMER (GPT) UNIT The GPT unit represents a very flexible multifunctional timer counter structure which may be used for many different time related tasks such as event timing and counting, pulse width and duty cycle measurements, ...

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G.P.T. (Cont’d) In addition to their basic operating modes, timers T2 and T4 may be configured as re- load or capture registers for timer T3. When used as capture or reload registers, tim- ers T2 and T4 are stopped. The ...

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ST10F166 G.P.T. (Cont’d) Figure 8. GPT1 Block Diagram System Clock n /2 n=3... osc T2 Mode T2in-P3.7 Control System Clock n /2 n=3... osc Mode Control T3in-P3.6 T3Eud-P3.4 T4 T4in-P3.5 Mode Control System ...

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SOFTWARE DESCRIPTION Addressing Modes The ST10F166 offers different powerful addressing modes to facilitate rapid access on word, byte and bit data specify the destination address of a branch instruc- tion. The addressing modes are subdivided in six ...

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ST10F166 Immediate data: these data are represented in the instruction formats by either 3,4 bits. Branch target addressing modes: to specify the destination address and segment of jump or call instructions, relative, absolute and indirect modes can be ...

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Software Description (Cont’d) Table 6. Addressing Mode Summary Addressing Mode 3 bit Immediate Data 4 bit Immediate Data 8 bit Immediate Data 16 bit Immediate Data 8 bit Immediate Mask GPR register direct SFR or GPR register direct Memory direct ...

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ST10F166 16 INSTRUCTION SET SUMMARY The table below lists the instructions of the ST10F166 in a condensed way. The various addressing modes that can be used with a specific instruction, the oper- ation of the instructions, parameters for conditional execution ...

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Instruction Set Summary (Cont’d) Mnemonic Description MOVBS Move byte operand to word operand with sign extension MOVBZ Move byte operand to word operand. with zero extension JMPA, JMPI, JMPR Jump absolute/indirect/relative if condition is met JMPS Jump absolute to a ...

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ST10F166 17 SPECIAL FUNCTION REGISTER OVERVIEW The following table lists all SFRs which are implemented in the ST10F166 in alpha- betical order. Bit-addressable SFRs are marked with the letter “b” in column “Name”. An SFR can be specified via its ...

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Special Function Register Overview (Cont’d) Physical 8-Bit Name Address Address CC9 FE92h 49h CC9IC b FF8Ah C5h CC10 FE94h 4Ah CC10IC b FF8Ch C6h CC11 FE96h 4Bh CC11IC b FF8Eh C7h CC12 FE98h 4Ch CC12IC b FF90h C8h CC13 FE9Ah ...

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ST10F166 Special Function Register Overview (Cont’d) Physical 8-Bit Name Address Address P1 b FF04h 82h P2 b FFC0h E0h P3 b FFC4h E2h P4 b FF08h 84h P5 b FFA2h D1h PECC0 FEC0h 60h PECC1 FEC2h 61h PECC2 FEC4h 62h ...

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Special Function Register Overview (Cont’d) Physical 8-Bit Name Address Address T0IC b FF9Ch CEh T0REL FE54h 2Ah T1 FE52h 29h T1IC b FF9Eh CFh T1REL FE56h 2Bh T2 FE40h 20h T2CON b FF40h A0h T2IC b FF60h B0h T3 FE42h ...

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ST10F166 18 ELECTRICAL CHARACTERISTICS 18.1 Absolute Maximum Ratings Ambient temperature under bias (T Storage temperature ( ...

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DC Characteristics +70 C for ST10F166/166-16 A Parameter Input low voltage EBC1 Input low voltage V (all except EBC1 ...

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ST10F166 DC Characteristics (Cont’d) Parameter 6) Pin capacitance C (digital inputs/outputs) Power supply current I Idle mode supply current I Power-down mode supply current read current write current during write/read ...

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DC Characteristics (Cont’d) Figure 10. Supply/Idle Current as a Function of Operating Frequency Current (mA) 250 200 150 100 Iid CPU Frequency (MHz) ST10F166 20 VR02049 40/62 ...

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ST10F166 18.4 A/D Converter Characteristics +70 C for ST10F166/166- AREF CC Parameter Analog input voltage range ...

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Testing Waveforms Figure 11. Input Output Waveforms AC inputs during testing are driven at 2.4 V for a logic ‘1’ and 0.4 V for a logic ‘0’. Timing measurements are made at V Figure 12. Float Waveforms For timing ...

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ST10F166 18.7 AC Characteristics The specification of the timings depends on the CPU clock signal that is used in the respective device. In this regard the specification for the ST10F166 and the ST10F166-16 are different. While the ST10F166-16 directly uses ...

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AC Characteristics (Cont’d) External Clock Drive XTAL1 for the ST10F166- + Parameter Symbol Oscillator period CLP SR High time TCL SR H ...

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ST10F166 AC Characteristics (Cont’d) Multiplexed Bus for the ST10F166 = + (for Port 0, Port 1, Port 4, ALE, RD, WR, BHE, CLKOUT) ...

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AC Characteristics (Cont’d) Multiplexed Bus for the ST10F166- (for Port 0, Port 1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100 pF L ALE cycle time ...

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ST10F166 AC Characteristics (Cont’d) Figure 15. External Memory Cycle: Multiplexed Bus, With Read/Write Delay, Normal ALE t 5 ALE A17-A16 (A15-A8) BHE t 6 Read Cycle BUS Address RD Write Cycle BUS Address WR 47/ ...

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AC Characteristics (Cont’d) Figure 16. Ext. Memory Cycle: Multiplexed Bus, With Read/Write Delay, Extended ALE t 5 ALE A17-A16 (A15-A8) BHE t 6 Read Cycle BUS Address RD Write Cycle BUS Address ...

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ST10F166 AC Characteristics (Cont’d) Figure 17. External Memory Cycle: Multiplexed Bus, No Read/Write Delay, Normal ALE t 5 ALE A17-A16 (A15-A8) BHE t 6 Read Cycle BUS Address t RD Write Cycle BUS Address t WR 49/ ...

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AC Characteristics (Cont’d) Figure 18. Ext. Memory Cycle: Multiplexed Bus, No Read/Write Delay, Extended ALE t 5 ALE A17-A16 (A15-A8) BHE t 6 Read Cycle BUS Address RD Write Cycle BUS Address ...

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ST10F166 AC Characteristics (Cont’d) Demultiplexed Bus for the ST10F166 + (for Port 0, Port 1, Port 4, ALE, RD, WR, BHE, ...

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AC Characteristics (Cont’d) Demultiplexed Bus for the ST10F166- + (for Port 0, Port 1, Port 4, ALE, RD, WR, BHE, CLKOUT) ...

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ST10F166 AC Characteristics (Cont’d) Figure 19. Ext. Memory Cycle: Demultiplexed Bus, With Read/Write Delay, Normal ALE t 5 ALE A17-A16 A15-A0 BHE t 6 Read Cycle BUS (D15-D8) D7-D0 RD Write Cycle BUS (D15-D8) D7-D0 WR 53/ ...

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AC Characteristics (Cont’d) Figure 20. Ext. Mem. Cycle: Demultiplexed Bus, With Read/Write Delay, Extended ALE t 5 ALE A17-A16 A15-A0 BHE t 6 Read Cycle BUS (D15-D8) D7-D0 RD Write Cycle BUS (D15-D8) D7- ...

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ST10F166 AC Characteristics (Cont’d) Figure 21. Ext. Memory Cycle: Demultiplexed Bus, No Read/Write Delay, Normal ALE t 5 ALE A17-A16 A15-A0 BHE t 6 Read Cycle BUS (D15-D8) D7- Write Cycle BUS (D15-D8) D7- 55/62 t ...

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AC Characteristics (Cont’d) Figure 22. Ext. Memory Cycle: Demultiplexed Bus, No Read/Write Delay, Extended ALE t 5 ALE A17-A16 A15-A0 BHE t 6 Read Cycle BUS (D15-D8) D7-D0 RD Write Cycle BUS (D15-D8) D7- ...

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ST10F166 AC Characteristics (Cont’d) CLKOUT and READY for ST10F166 + (for Port 0, Port 1, Port 4, ALE, RD, WR, BHE, ...

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AC Characteristics (Cont’d) CLKOUT and READY for ST10F166- + (for Port 0, Port 1, Port 4, ALE, RD, WR, BHE, CLKOUT) ...

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ST10F166 AC Characteristics (Cont’d) Figure 23. CLKOUT and READY Running cycle CLKOUT ALE Command 2) RD Sync READY Async 3) READY ...

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AC Characteristics (Cont’d) External Bus Arbitration +70 C for ST10R165 A C (for Port 0, Port 1, Port 4, ALE, RD, WR, BHE, CLKOUT) ...

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ST10F166 AC Characteristics (Cont’d) Figure 25. External Bus Arbitration, (Regaining the Bus) CLKOUT t HOLD HLDA t 62 BREQ Other Signals Notes: 1) This is the last chance for BREQ to trigger the indicated regain-sequence. Even if BREQ is activated ...

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... Package ST10F166BQ1 PQFP-100 ST10F166BQ1-16 Information furnished is believed to be accurate and reliable. However, SGS-TH OMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specification mentioned in this publication are subject to change without notice ...