SAA7105H NXP Semiconductors, SAA7105H Datasheet
SAA7105H
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SAA7105H Summary of contents
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... DATA SHEET SAA7104H; SAA7105H Digital video encoder Product specification INTEGRATED CIRCUITS 2004 Mar 04 ...
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... RGB processor 7.14 Triple DAC 7.15 HD data path 7.16 Timing generator 7.17 Pattern generator for HD sync pulses 2 7.18 I C-bus interface 7.19 Power-down modes 7.20 Programming the SAA7104H; SAA7105H 7.21 Input levels and formats 7.22 Bit allocation map 2 7.23 I C-bus format 7.24 Slave receiver 7.25 Slave transmitter 2004 Mar 04 SAA7104H; SAA7105H 8 BOUNDARY SCAN TEST 8 ...
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... RGB Look-Up Table (LUT) Support for hardware cursor HDTV up to 1920 1080 interlaced and 1280 progressive, including 3-level sync pulses 2004 Mar 04 SAA7104H; SAA7105H Programmable border colour of underscan area Programmable 5 line anti-flicker filter On-chip 27 MHz crystal oscillator (3rd-harmonic or fundamental 27 MHz crystal) 2 ...
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... Philips Semiconductors Digital video encoder 2 GENERAL DESCRIPTION The SAA7104H; SAA7105H is an advanced next-generation video encoder which converts PC graphics data at maximum 1280 (optionally 1920 1080 interlaced) to PAL (50 Hz) or NTSC (60 Hz) video signals. A programmable scaler and anti-flicker filter (maximum 5 lines) ensures properly sized and flicker-free TV display as CVBS or S-video output ...
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... FIFO PD11 to INPUT PD0 FORMATTER UPSAMPLING DECIMATOR HORIZONTAL SCALER PIXCLKI 19 PIXCLKI BORDER FIFO GENERATOR 36 LLC SAA7104H 38 SRES SAA7105H 27 PIXEL CLOCK CRYSTAL PIXCLKO SYNTHESIZER OSCILLATOR 1, 16 XTALI n.c. RTCI 27 MHz SSA2 DDD1 ...
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... VGC (optional input); note 3 not connected not connected not connected not connected not connected if HIGH (default by pull-up): LLC, RTCI and SRES are outputs; if LOW: LLC, RTCI and SRES are inputs I/O line-locked clock I/O real-time control input 6 Product specification SAA7104H; SAA7105H DESCRIPTION ...
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... Tables for pin assignment MSB 1 with C -Y see Tables for pin assignment MSB with C -Y see Tables for pin assignment Product specification SAA7104H; SAA7105H DESCRIPTION CVBS signal R or CVBS signal B resistor to analog ground ...
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... V SSD1 7 RESET 8 9 TMS TDO 10 TCK 11 V DDD2 12 V SSD2 13 SCL 14 SDA 15 n.c. 16 2004 Mar 04 SAA7104H SAA7105H Fig.2 Pin configuration. 8 Product specification SAA7104H; SAA7105H 48 V SSA1 47 DUMP 46 RSET 45 BLUE_CB_CVBS 44 V DDA2 43 V DDA1 42 GREEN_VBS_CVBS 41 RED_CR_C_CVBS 40 HSM_CSYNC 39 VSM 38 SRES 37 RTCI 36 LLC ...
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... PC-DVD; for that the anti-flicker filter, and in most cases the scaler, will simply be bypassed. Besides the applications for video output, the SAA7104H; SAA7105H can also be used for generating a kind of auxiliary VGA output, when the RGB non-interlaced input signal is fed to the DACs. This may be of interest for example, when the graphics controller provides a second graphics window at its video output port ...
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... The first index is the , to a common internal column, followed by the row; index 0,0 is the upper left corner. 2 C-bus control 10 Product specification SAA7104H; SAA7105H -C is being applied Mbyte/s data stream the input data rate. An optional RGB LUT ...
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... A special case is ... ... XINC = 0, this sets the scaling factor to 1. row 31 row 31 If the SAA7104H; SAA7105H input data is in accordance column column with “ITU-R BT.656” , the scaler enters another mode this event, XINC needs to be set to 2048 for a scaling ...
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... CVBS or separate Y and C signals. Input to the encoder MHz clock (e.g. DVD), is either originated from computer graphics at pixel clock, fed through the FIFO and border generator ITU-R BT.656 style signal. 12 Product specification SAA7104H; SAA7105H 2 C-bus control and C baseband signals ...
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... Y and colour difference signals and 2 times oversampling for luminance and 4 times oversampling for colour difference signals is performed. The transfer curves of luminance and colour difference components of RGB are illustrated in Figs 8 and 9. 13 Product specification SAA7104H; SAA7105H IDEO ROGRAMMING YSTEM ...
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... In addition, an automatic sense mode can be activated which indicates a 75 outputs at the dedicated interrupt pin TVD. If the SAA7104H; SAA7105H is required to drive a second (auxiliary) VGA monitor or an HDTV set, the DACs receive the signal coming from the HD data path. In this event, the DACs are clocked at the incoming PIXCLKI instead of the 27 MHz crystal clock used in the video encoder ...
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... The sync engines flexibility is achieved by using a sequence of linked lists carrying the properties for the 2004 Mar 04 SAA7104H; SAA7105H image, the lines as well as fractions of lines. Figure 3 illustrates the context between the various tables. The first table serves as an array to hold the correct sequence of lines that compose the synchronization raster ...
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Acrobat reader. white to force landscape pages to be ... handbook, full pagewidth 4-bit line type index line type pointer 8 2-bit value VALUE ...
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... Reading of the arrays is possible but all address pointers must be initialized before the next write operation. value( value(3); (subtract 1 from real duration) value( value(3) value(3) + 960 value(0) + 960 value( value( value(3) value(3) + 960 value(3) + 960 17 Product specification SAA7104H; SAA7105H COMMENT value( value(3) value( value(3) sync-black-null-black) ...
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... Because there is no frame memory isolating the data streams, restrictions apply to the input frame timings. Input and output processing of the SAA7104H; SAA7105H are only coupled through the vertical frequencies. In master mode, the encoder provides a vertical sync and an odd/even pulse to the input processing ...
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... The only constraint is that the horizontal blanking has at least 10 clock pulses. 2004 Mar 04 SAA7104H; SAA7105H The required pixel clock frequency can be determined in the following way: Due to the limited internal FIFO size, the input path has to provide all pixels in the same time frame as the encoders vertical active time ...
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... The SAA7104H; SAA7105H has special input cells for the VGC port. They operate at a wider supply voltage range and have a strict input threshold at speed of these cells, the EIDIV bit needs to be set to logic 1 ...
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... R R0/C 0 PD0 R G7/Y7 Table 11 Pin assignment for input format 3 G6/ 8-BIT NON-INTERLACED C G5/Y5 G4/Y4 PIN PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 21 Product specification SAA7104H; SAA7105H FALLING PIN CLOCK EDGE FALLING PIN CLOCK EDGE ...
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... Y3(1) R PD5 C 2(0) Y2(1) R PD4 C 1(0) Y1(1) R PD3 C 0(0) Y0(1) R PD2 PD1 PD0 RISING CLOCK EDGE Product specification SAA7104H; SAA7105H RGB/C -Y FALLING PIN CLOCK EDGE G4/Y4 G3/Y3 G2/ G0/ RISING CLOCK EDGE ...
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Acrobat reader. white to force landscape pages to be ... 7.22 Bit allocation map Table 15 Slave receiver (slave address 88H) SUB REGISTER FUNCTION ...
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Acrobat reader. white to force landscape pages to be ... SUB REGISTER FUNCTION ADDR. (HEX) Gain U 5B GAINU7 Gain V 5C GAINV7 Gain ...
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Acrobat reader. white to force landscape pages to be ... SUB REGISTER FUNCTION ADDR. (HEX) TTX even request vertical end 79 TTXEVE7 First active ...
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Acrobat reader. white to force landscape pages to be ... SUB REGISTER FUNCTION ADDR. (HEX) Blank enable for NI-bypass, A1 BLEN vertical line skip ...
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Acrobat reader. white to force landscape pages to be ... SUB REGISTER FUNCTION ADDR. (HEX) Input path control FD LUTOFF Cursor bit map FE ...
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... If more than 1 byte of DATA is transmitted, then auto-increment of the subaddress is performed. 2004 Mar 04 SUBADDRESS A DATA 0 RAM ADDRESS A DATA 00 A RAM ADDRESS A RAM ADDRESS A DATA DESCRIPTION 28 Product specification SAA7104H; SAA7105H A -------- DATA n A DATA 01 A -------- DATA n DATA 0 A -------- DATA n A DATA 0G A DATA ...
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... BLUE DAC; default after reset is 1FH for output of CVBS signal 00000b 0.585 V to 11111b Table 26 Subaddress 1AH DATA BYTE MSMT monitor sense mode threshold for DAC output voltage, should be set to 70 2004 Mar 04 SAA7104H; SAA7105H DESCRIPTION GAIN (%) ...
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... DATA BYTE LEVEL BS starting point of burst in clock cycles 2004 Mar 04 DESCRIPTION DESCRIPTION DESCRIPTION PAL (21H); default after reset if strapping pin FSVGC tied to HIGH NTSC (19H); default after reset if strapping pin FSVGC tied to LOW 30 Product specification SAA7104H; SAA7105H REMARKS ...
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... HIGH impulse resets synchronization of the encoder (first field, first line) PAL (1DH); default after reset if strapping pin FSVGC tied to HIGH NTSC (1DH); default after reset if strapping pin FSVGC tied to LOW DESCRIPTION DESCRIPTION 31 Product specification SAA7104H; SAA7105H REMARKS ) signal B ) signal R ...
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... Suggested nominal value = 0, depending on external application. GCD4 to GCD0 Gain colour difference of RGB (C (1 application. 2004 Mar 04 DESCRIPTION DESCRIPTION DESCRIPTION , Y and and Suggested nominal value = 0, depending on external Product specification SAA7104H; SAA7105H 16 ) output, ranging from ( output, ranging from ...
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... VPS14 fourteenth byte of video programming system data 2004 Mar 04 DESCRIPTION to RGB dematrix is active; default after reset R to RGB dematrix is bypassed R DESCRIPTION DESCRIPTION 33 Product specification SAA7104H; SAA7105H REMARKS in line 16; LSB first; all other bytes are not relevant for VPS ...
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... BLCKL = 63 (3FH); note 1 output black level = 49 IRE white-to-sync = 143 IRE; recommended value: BLCKL = 51 (33H) note 2 BLCKL = 0; note 2 output black level = 27 IRE BLCKL = 63 (3FH); note 2 output black level = 47 IRE 2/6.29 + 28.9. 2/6.18 + 26.5. 34 Product specification SAA7104H; SAA7105H RESULT REMARKS nominal to +2.16 nominal nominal to +2.04 nominal REMARKS nominal to +1.55 nominal nominal to +1.46 ...
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... BLNNL = 0; note 2 BLNNL = 63 (3FH); note 2 2/6.29 + 25.4. 2/6.18 + 25.9; default after reset: 35H. DESCRIPTION DESCRIPTION 35 Product specification SAA7104H; SAA7105H REMARKS recommended value: BLNNL = 46 (2EH) output blanking level = 25 IRE output blanking level = 45 IRE recommended value: BLNNL = 53 (35H) output blanking level = 26 IRE output blanking level = 46 IRE ...
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... IRE; PAL encoding BSTA = 0 to 2.82 white-to-black = 100 IRE; burst = 43 IRE; NTSC encoding BSTA = 0 to 1.90 white-to-black = 100 IRE; burst = 43 IRE; PAL encoding BSTA = 0 to 3.02 36 Product specification SAA7104H; SAA7105H 2 C-bus address CONDITIONS REMARKS recommended value: BSTA = 63 (3FH) nominal recommended value: BSTA = 45 (2DH) ...
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... LSBs of the respective bytes are encoded immediately after run-in and framing code, the MSBs of the respective bytes have to carry the parity bit, in accordance with the definition of line 21 encoding format. DESCRIPTION DESCRIPTION 37 SAA7104H; SAA7105H CONDITIONS FSC3 = most significant byte fsc = ...
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... Table 57 Logic levels and function of CCEN DATA BYTE CCEN1 CCEN0 0 0 line 21 encoding off; default after reset 0 1 enables encoding in field 1 (odd enables encoding in field 2 (even enables encoding in both fields 2004 Mar 04 SAA7104H; SAA7105H DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION 38 Product specification ...
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... TTXOVE for other systems 2004 Mar 04 DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION 39 Product specification SAA7104H; SAA7105H REMARKS TTXHS = 42H; is default after reset if strapped to PAL TTXHS = 54H; is default after reset if strapped to NTSC REMARKS minimum value: TTXHD = 2; is default after reset REMARKS TTXOVS = 05H ...
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... DESCRIPTION DESCRIPTION MHz nominal, e.g. 640 XTAL XTAL 40 Product specification SAA7104H; SAA7105H REMARKS TTXEVS = 04H; is default after reset if strapped to PAL TTXEVS = 05H; is default after reset if strapped to NTSC TTXEVE = 16H; is default after reset if strapped to PAL TTXEVE = 10H; is default after reset if strapped to NTSC 480 to NTSC M: PCL = 20F63BH ...
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... FIFO internal transfers; nominal value is 8; default after reset Table 72 Subaddresses 90H and 94H DATA BYTE XOFS horizontal offset; defines the number of PIXCLKs from horizontal sync (HSVGC) output to composite blanking (CBO) output 2004 Mar 04 SAA7104H; SAA7105H DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION 41 ...
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... CBO signal (HIGH during active video) 1 inverted polarity of CBO signal (LOW during active video) SLAVE 0 the SAA7104H; SAA7105H is timing master to the graphics controller 1 the SAA7104H; SAA7105H is timing slave to the graphics controller ILC 0 if hardware cursor insertion is active, set LOW for non-interlaced input signals ...
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... HLEN horizontal length; Table 80 Subaddress 99H DATA BYTE IDEL input delay; defines the distance in PIXCLKs between the active edge of CBO and the first received valid pixel 2004 Mar 04 DESCRIPTION number of PIXCLKs HLEN ---------------------------------------------------- - 1 = – line DESCRIPTION 43 Product specification SAA7104H; SAA7105H DESCRIPTION ...
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... Table 87 Subaddresses A2H to A4H DATA BYTE BCY, BCU luminance and colour difference portion of border colour in underscan area and BCV 2004 Mar 04 SAA7104H; SAA7105H DESCRIPTION number of output pixels ------------------------------------------------------------- - line XINC = ------------------------------------------------------------- - number of input pixels ...
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... DESCRIPTION DESCRIPTION HLC6 HLC5 HLC4 HLT2 HLT1 HLT0 DESCRIPTION DESCRIPTION HLP11 HLP10 HLP31 HLP30 HLP51 HLP50 HLP71 HLP70 DESCRIPTION 45 Product specification SAA7104H; SAA7105H 1 with the HLC3 HLC2 HLC1 0 0 HLC9 0 HLP02 HLP01 0 HLP22 HLP21 0 HLP42 HLP41 0 HLP62 HLP61 HLC0 HLC8 1 ...
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... HPV11 HPV10 HPD25 HPD24 HPV21 HPV20 HPD35 HPD34 HPV31 HPV30 DESCRIPTION DESCRIPTION HPVE5 HPVE4 DESCRIPTION DESCRIPTION DESCRIPTION 46 Product specification SAA7104H; SAA7105H HPD03 HPD02 HPD01 0 0 HPD09 HPD13 HPD12 HPD11 0 0 HPD19 HPD23 HPD22 HPD21 0 0 HPD29 HPD33 HPD32 HPD31 ...
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... RED, GREEN and BLUE portion of auxiliary cursor colour and AUXB Table 104 Subaddresses F9H and FAH DATA BYTE XCP horizontal cursor position Table 105 Subaddress FAH DATA BYTE XHS horizontal hot spot of cursor 2004 Mar 04 SAA7104H; SAA7105H DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION DESCRIPTION 47 Product specification ...
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... In subaddresses 5BH, 5CH, 5DH, 5EH, 62H and D3H all IRE values are rounded up. 2004 Mar 04 DESCRIPTION DESCRIPTION DESCRIPTION -Y-C matrix is active R B -Y-C matrix is bypassed R B DESCRIPTION DESCRIPTION 48 Product specification SAA7104H; SAA7105H -Y -Y -Y-C (ITU-R BT.656, 27 MHz clock -Y-C (special bit ordering ...
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... O_E 1 during even field 0 during odd field Table 113 Subaddress 1CH DATA BYTE CID chip ID of SAA7104H = 04H; chip ID of SAA7105H = 05H Table 114 Subaddress 80H LOGIC DATA BYTE LEVEL IFERR 0 normal FIFO state 1 input FIFO overflow/underflow has occurred ...
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... SCBW = 1. (2) SCBW = 0. handbook, halfpage (1) SCBW = 1. (2) SCBW = 0. 2004 Mar 04 ( Fig.4 Chrominance transfer characteristic (dB) 0 (1) ( 0.4 0.8 1.2 f (MHz) Fig.5 Chrominance transfer characteristic 2. 50 Product specification SAA7104H; SAA7105H MBE737 (MHz) MBE735 1.6 14 ...
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... Fig.6 Luminance transfer characteristic 1 (excluding scaler). handbook, halfpage (1) CCRS1 = 0; CCRS0 = 0. Fig.7 Luminance transfer characteristic 2(excluding scaler). 2004 Mar 04 (4) (2) (3) ( (dB) ( Product specification SAA7104H; SAA7105H MBE736 6 f (MHz) MGD672 14 f (MHz) ...
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... Fig.8 Luminance transfer characteristic in RGB (excluding scaler). handbook, full pagewidth (dB Fig.9 Colour difference transfer characteristic in RGB (excluding scaler). 2004 Mar Product specification SAA7104H; SAA7105H MGB708 (MHz) MGB706 (MHz) ...
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... The 5 special pins are Test Mode Select (TMS), Test Clock (TCK), Test Reset (TRST), Test Data Input (TDI) and Test Data Output (TDO). Table 115 BST instructions supported by the SAA7104H; SAA7105H INSTRUCTION BYPASS This mandatory instruction provides a minimum length serial path (1 bit) between TDI and TDO when no test operation of the component is required ...
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... SAA7105H. Fig.10 32 bits of identification code. CONDITIONS outputs in 3-state outputs in 3-state; note 1 and V SSA(n) SSD(n) human body model; note 2 machine model; note 3 54 Product specification SAA7104H; SAA7105H LSB 1 0 TDO 1 00000010101 11-bit manufacturer identification MHC568 LSB 1 0 TDO 1 00000010101 ...
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... An ample copper area direct under the SAA7104H; SAA7105H with a number of through-hole plating, which connect to the ground layer (four-layer board: second layer), can also reduce the effective R addition the usage of soldering glue with a high thermal conductance after curing is recommended. ...
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... CLKO2 note 4 note 4 pins PD11 to PD0, RTCI and TTX_SRES pins PD11 to PD0, RTCI and TTX_SRES pins HSVGC, VSVGC and FSVGC; note 6 pins HSVGC, VSVGC and FSVGC; note 6 note 7 56 Product specification SAA7104H; SAA7105H MIN. TYP. MAX. 0 0.1 0 0.4 0 0.4 V 0.1 V DDD1 DDD1 2 ...
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... FSVGC and CBO pins TDO, 3 TTXRQ_XCLKO2, VSM and HSM_CSYNC pins TDO, TTXRQ_XCLKO2, VSM and HSM_CSYNC see Table 116 see Table 116 see Table 116 see Table 116 3 dB; note 8 57 Product specification SAA7104H; SAA7105H MIN. TYP. MAX 1.5 1.8 fF 3.5 4 ...
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... If an internal oscillator is used, crystal deviation of nominal frequency is directly proportional to the deviation of subcarrier frequency and line/field frequency ------------------------------------------------ 3 dB – ext 2004 Mar 100 mV for HIGH and / V 2 DDD2 is generated on chip. with R = 37.5 and (typical). L ext 58 Product specification SAA7104H; SAA7105H 100 mV for LOW. ...
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... Mar 04 T PIXCLK t HIGH HD;DAT t HD;DAT t SU;DAT t o(d) t o(h) Fig.11 Input/output timing specification 1. t HD;DAT t o(d) t o(h) Fig.12 Input/output timing specification 2. 59 Product specification SAA7104H; SAA7105H V OH 0.5V DDD1 0.5V DDD1 SU;DAT MHC567 V IH 0.5V DDD1 ...
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... Philips Semiconductors Digital video encoder handbook, full pagewidth HSVGC CBO PD handbook, full pagewidth HSVGC VSVGC CBO 2004 Mar 04 XOFS IDEL XPIX HLEN Fig.13 Horizontal input timing. YOFS YPIX Fig.14 Vertical input timing. 60 Product specification SAA7104H; SAA7105H MHB905 MHB906 ...
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... Fig.15 Teletext timing. 61 Product specification SAA7104H; SAA7105H is the internally used insertion window for i(TTXW) 2 C-bus register settings. t i(TTXW MHB891 ...
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... H 27 MHz XTALI XTALO 51 50 SAA7104H SAA7105H SSA RSET 1 k AGND AGND Fig.16 Application circuit. 62 Product specification SAA7104H; SAA7105H supply 0.1 F AGND use one capacitor for each V DDA V DDA1 to V DDA3 43, 44, 52 VSM, HSM_CSYNC 39, 40 GREEN_VBS_CVBS 42 FLTR0 75 AGND AGND RED_CR_C_CVBS 41 ...
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... Philips Semiconductors Digital video encoder handbook, halfpage 2004 Mar 04 C16 120 pF L2 2.7 H C10 C13 390 pF 560 pF AGND JP11 JP12 FIN FILTER 1 = byp. ll act. Fig.17 FLTR0, FLTR1 and FLTR2 of Fig.16. 63 Product specification SAA7104H; SAA7105H L3 2.7 H FOUT MHB912 ...
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... With fundamental quartz and restricted drive level. When P is too high, a resistance R s Note: The decreased crystal amplitude results in a lower drive level but on the other hand the jitter performance will decrease. Fig.18 Oscillator application. 64 Product specification SAA7104H; SAA7105H SAA7104H SAA7105H 51 50 XTALI XTALO 27.00 MHz ...
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... Mar 04 SAA7104H; SAA7105H Tables for example a standard PAL or NTSC signal) conditions occupy different conversion ranges, as indicated in Table 116 for a By setting the reference currents of the DACs as shown in Table 116, standard compliant amplitudes can be achieved for all signal combinations ...
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... scale (1) ( 0.45 0.23 14.1 14.1 17.45 17.45 0.8 0.30 0.13 13.9 13.9 16.95 16.95 REFERENCES JEDEC JEITA MS-022 66 SAA7104H; SAA7105H detail 1.03 1.2 1.6 0.16 0.16 0.1 0.73 0.8 EUROPEAN PROJECTION Product specification SOT393 (1) ( ...
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... Contact time must be limited to 10 seconds 300 C. When using a dedicated tool, all other leads can be soldered in one operation within seconds between 270 and 320 C. 67 Product specification SAA7104H; SAA7105H ...
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... However, the image sensor package can be mounted by the client on a flex foil by using a hot bar soldering process. The appropriate soldering profile can be provided on request. 9. Hot bar or manual soldering is suitable for PMFP packages. 2004 Mar 04 (1) (3) , TFBGA, (8) 68 Product specification SAA7104H; SAA7105H SOLDERING METHOD WAVE REFLOW not suitable suitable (4) not suitable suitable suitable ...
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... Product specification SAA7104H; SAA7105H DEFINITION These products are not Philips Semiconductors ...
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... Philips. This specification can be ordered using the code 9398 393 40011. 2004 Mar 04 C COMPONENTS 2 C components conveys a license under the Philips’ system provided the system conforms to the I 70 Product specification SAA7104H; SAA7105H 2 C patent to use the 2 C specification defined by ...
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Philips Semiconductors – a worldwide company Contact information For additional information please visit http://www.semiconductors.philips.com. For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com. © Koninklijke Philips Electronics N.V. 2004 All rights are reserved. Reproduction in whole or in part is prohibited ...