STA529Q STMicroelectronics, STA529Q Datasheet - Page 32

• Manufacturer Part Number: STA529Q
• Description: IC AMP 2X100MW CLASS D 52VFQFPN
• Manufacturer: STMicroelectronics
• Series: Sound Terminal™r
• Type: Class Dr

Specifications of STA529Q

• Output Type: 2-Channel (Stereo)
• Max Output Power X Channels @ Load: 100mW x 2 @ 16 Ohm
• Voltage - Supply: 1.5 V ~ 1.95 V
• Features: Depop, I²C, I²S, Mute, Volume Control
• Mounting Type: Surface Mount
• Package / Case: 52-VFQFN, 52-VFQFPN
• Ic Function: FFX Audio Codec Analogue & Digital Inputs, Class D Amplifier
• Brief Features: Up To 96dB Dynamic Range, FFX Class-D Driver
• Supply Voltage Range: 1.55V To 1.95V, 1.8V To 3.6V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-8879

I
10
10.1
10.2
10.3
10.4
10.5
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2
C interface
I
Data transition and change
Data changes on the SDA line must only occur when the SCL clock is low. SDA transition
while the clock is high is used to identify a start or stop condition.
Start condition
A start condition is identified by a high to low transition of the data bus SDA signal while the
clock signal SCL is stable in the high state. A start condition must precede any command for
data transfer.
Stop condition
A stop condition is identified by low to high transition of the data bus SDA signal while the
clock signal SCL is stable in the high state. A stop condition terminates communication
between the STA529 and the master bus.
Data input
During data input, the STA529 samples the SDA signal on the rising edge of clock SCL. For
correct device operation the SDA signal must be stable during the rising edge of the clock
and the data can change only when the SCL line is low.
Device addressing
To start communication between the master and the STA529, the master must initiate with a
start condition. Following this, the master sends 8 bits (MSB first) on the SDA line
corresponding to the device select address and read or write mode.
The 7 most significant bits are the device address identifiers, corresponding to the I
definition. In the STA529, the I
The 8th bit (LSB) identifies the read or write operation (R/W). It is set to 1 in read mode and
0 in write mode.
After the start condition, the STA529 waits for its device address on SDA. When a match is
found, it acknowledges the identification on SDA during the 9th bit time. The byte following
the device identification byte is the internal space address.
2
C interface
2
Doc ID 13095 Rev 2
C interface has the device address 0x34.
2
STA529
C bus