UPD78P4916GF-3BA NEC, UPD78P4916GF-3BA Datasheet
UPD78P4916GF-3BA
Available stocks
Related parts for UPD78P4916GF-3BA
UPD78P4916GF-3BA Summary of contents
Page 1
SINGLE-CHIP MICROCONTROLLER The PD78P4916 is one of the PD784915 subseries in the 78K/IV Series microcontrollers which incorporate a high-speed and high-performance 16-bit CPU. The PD78P4916 replaces mask ROM with one-time PROM and increases on-chip ROM and RAM capacity compared ...
Page 2
Series Products 78K/I Series PD78138 Subseries Enhanced peripheral hardware 2 78K/IV Series High-performance 16-bit CPU core High-speed operation On-chip analog circuit for VCR PD78148 Subseries PD78P4916 m PD784915 PD784915 Subseries Subseries ...
Page 3
Function List (1/2) Item Internal PROM capacity 62 Kbytes Internal RAM capacity 2048 bytes Operation clock 16 MHz (Internal clock: 8 MHz) Low frequency oscillation mode: 8 MHz (Internal clock: 8 MHz) Low power consumption mode: 32.768 kHz (Subsystem clock) ...
Page 4
Function List (2/2) Item Analog unit Interrupt External * Internal Standby function * Watch function Power supply voltage Package 4 Function • CTL amplifier • RECCTL driver (supports re-write operation) • DFG amplifier, DPG comparator, CFG amplifier • DPFG separator ...
Page 5
... RESET PTO02 22 PTO01 23 PTO00 24 P87/PTO11 25 P86/PTO10 26 P85/PWM3 27 P84/PWM2 28 P83/ROTC 29 P82/HASW Caution Connect the IC (Internally Connected) pin ...
Page 6
... CTLOUT1, CTLOUT2 : CTL Amplifier Output DFGIN : Analog Unit Input DPGIN : Analog Unit Input ENV : Envelope Input HASW : Head Amplifier Switch Output HWIN : Hardware Timer External Input IC : Internally Connected INTP0-INTP3 : Interrupt From Peripherals KEY0-KEY4 : Key Return NMI : Nonmaskable Interrupt 6 P00-P07 : Port0 P40-P47 : Port4 ...
Page 7
... Cautions (L) : Connect Connect to ground. SS OPEN : Leave this pin unconnected. RESET : Apply low level A16 : Address Bus Data Bus CE : Chip Enable OE : Output Enable PGM : Program ...
Page 8
Internal Block Diagram NMI Interrupt Control INTP0 - INTP3 PWM0 - PWM5 PTO00 - Super Timer PTO02 Unit PTO10, PTO11 VREFC REEL0IN REEL1IN CSYNCIN DFGIN DPGIN CFGIN CFGAMPO CFGCPIN CTLOUT1 CTLOUT2 CTLIN RECCTL+ RECCTL – CTLDLY Analog ...
Page 9
System Configuration Example • Camcorder Drum motor M Capstan motor M CTL head Loading motor M Composite sync signal Audio-video Video head switch signal processor Audio head switch Pseudo-vertical sync signal Remote control Signals from receive signal remote controller PC2800A ...
Page 10
Deck-type VCR DFG DFGIN DPGIN DPG Drum Driver PWM0 M motor CFG CFGIN Capstan M Driver PWM1 motor RECCTL+ CTL head RECCTL– Loading M Driver PWM2 motor Reel FG0 REEL0IN M Driver PWM3 Reel motors M Driver PWM4 Reel ...
Page 11
... 2 ...
Page 12
DIFFERENCES BETWEEN PD78P4916 AND PD784915, PD784916A * Other than the memory types, their capacities, and memory-related points, the functions of the three devices are identical: the PD78P4916 incorporates a one-time PROM that is rewritable by users, while the PD784915 ...
Page 13
PIN FUNCTION 2.1 Normal Operation Mode (1) Port Pins Pin Name Input/Output Alternate function P00 - P07 I/O Real-time output port P40 - P47 I/O P50 - P57 I/O P60 I/O P61 P62 P63 P64 P65 P66 P67 P70 ...
Page 14
... P70 - P77 Analog inputs for A/D converter – – CTL amplifier input capacitor – CTL amplifier output – Logic input/CTL amplifier output – RECCTL output/PBCTL input – External time-constant connection (to rewrite RECCTL) – AC ground for VREF amplifier – Non-maskable interrupt request input PD78P4916 ...
Page 15
... Buzzer output P65 Hardware timer external input – Reset input – Crystal resonator connection for main system clock oscillation – Crystal resonator connection for subsystem clock oscillation Crystal resonator connection for clock oscillation of watch – Positive power supply for analog unit – ...
Page 16
... Pin I/O Circuits and Recommended Connection of Unused Pins Table 2-1 shows the input/output circuit types of the device’s pins and the recommended connection of the pins which are unnecessary to the user’s application. The circuit diagrams for the I/O circuits are shown in Figure 2-1. Table 2-1. Pin I/O Circuits and Recommended Connection of Unused Pins (1/2) ...
Page 17
... Table 2-1. Pin I/O Circuits and Recommended Connection of Unused Pins (2/2) Pins I/O circuit types DFGIN — DPGIN CFGIN, CFGCPIN CSYNCIN REEL0IN/INTP3, REEL1IN CTLOUT1 — CTLOUT2 — CFGAMPO — CTLIN — VREFC CTLDLY PWM0, PWM1 3 PTO00-PTO02 NMI 2 INTP0 INTP1, INTP2 2 — DD1 DD2 ...
Page 18
Figure 2-1. Pin I/O Circuit Diagrams (1/2) Type 2 IN Schmitt triggered input with hysteresis characteristics. Type 2 P-ch IN Schmitt triggered input with hysteresis characteristics. Type P-ch data N-ch Type 4 V data P-ch ...
Page 19
Figure 2-1. Pin I/O Circuit Diagrams (2/2) Type 9 P-ch Comparator IN N-ch V (Threshold voltage) REF input enable PD78P4916 19 ...
Page 20
INTERNAL MEMORY CAPACITY SELECT REGISTER (IMS) Internal memory capacity select register (IMS) specifies the effective area of on-chip memory (PROM, RAM) of the PD78P4916. Setting this register is required when the capacity of the ROM or RAM in the ...
Page 21
PROM PROGRAMMING The PD78P4916 has on-chip 62-Kbyte PROM as the program memory. The PROM programming mode is entered by setting V , IC/V , and RESET pins as specified. For the settings of the unused pins in this mode, ...
Page 22
... Program inhibit mode When the OE pins, V pins, and D0-D7 pins of two or more PD78P4916s are connected in parallel, use PP program inhibit mode to write data to one of those devices. Programming is executed in the page programming mode or byte programming mode as mentioned above. At that time, data is not programmed to a device for which high level voltage is applied to the PGM pin ...
Page 23
PROM Write Procedure Figure 4-1. Flowchart in Page Programming Mode V Address = Address + 1 0.1-ms programming pulse No V Pass Remarks Start address End address of the program Start Address = ...
Page 24
Figure 4-2. Operation Timing in Page Programming Mode Page data latch Address input A2 - A16 A0 Data input +1 ...
Page 25
Figure 4-3. Flowchart in Byte Programming Mode 0.1-ms programming pulse Address = Address + 1 No Address = 4 Pass Verify all bytes Write operation ...
Page 26
Figure 4-4. Operation Timing in Byte Programming Mode Programming A0 - A16 Hi Data input +1 PGM V ...
Page 27
... 4.4 Screening One-time PROM Versions The one-time PROM version ( PD78P4916GF-3BA) cannot be completely tested by NEC for shipment because of its structure. For screening recommended to verify PROM after storing the necessary data under the following conditions: Storage Temperature pin. Connect other unused pins as specified in “(2) PROM PP Figure 4-5 ...
Page 28
ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings (T A Parameter Symbol Supply voltage DD1 AV DD2 AV SS1 AV SS2 Input voltage V I Analog input voltage V IAN (ANI0-ANI11) Output voltage V O Output current, low ...
Page 29
Oscillator Characteristics (Main Clock) (T Resonator Recommended circuit Crystal resonator X1 C1 Oscillator Characteristics (Subclock) (T Resonator Recommended circuit Crystal resonator XT1 C1 Caution When using the main system clock and subsystem clock oscillators, wiring in the area enclosed with ...
Page 30
... STOP mode V = 2.5 V DDDR Pull-up resistor Notes 1. RESET, IC, NMI, INTP0-INTP2, P61/SCK1/BUZ, P63/SI1, SCK2, SI2/BUSY, P65/HWIN, P91/KEY0-P95/KEY4. 2. P46, P47 3. When subclock is suspended at STOP mode, disconnect feedback resistor and connect XT1 pin to the V potential 4 Conditions DD ...
Page 31
AC Characteristics CPU and peripheral unit operation clocks (T Parameter Symbol CPU operation clock cycle time t CLK Peripheral unit operation clock t CLK1 cycle time Serial interface (1) SIOn –10 to +70 ˚C, ...
Page 32
Other Operations (T = –10 to +70 ˚ Parameter Symbol Timer unit input low level width t Timer unit input high level width t Timer unit input signal valid edge t input cycle CSYNCIN low level width t ...
Page 33
Clock Output Operation (T = –10 to +70 ˚ Parameter Symbol CLO cycle time t CLO low level width CLO high level width CLO rising time CLO falling time Data Retention Characteristics (T = –10 to +70 ˚C, ...
Page 34
VREF Amplifier ( ˚ Parameter Symbol Reference voltage V Charge current Note RECCTL+, RECCTL–, CFGIN, CFGCPIN, DFGIN, DPGIN, CSYNCIN, REEL0IN, REEL1IN CTL Amplifier ( ˚ ...
Page 35
... Input protect resistance R Comparator high voltage V Comparator low voltage V Caution The resistance of the pin to be connected to the DFGIN pin must be below the resistance is higher than the limit, the DFG amplifier may oscillate. DPG Comparator (AC Coupling Parameter Symbol Input impedance ...
Page 36
Three-value divider ( ˚ Parameter Symbol Input impedance Z Comparator high voltage V Comparator low voltage V CSYNC Comparator (AC Coupling) (T Parameter Symbol Input impedance Z Comparator high voltage V Comparator low voltage V ...
Page 37
Timing Waveform AC timing test point 0 2 0.8 V Serial Transfer Timing (SIOn WSKL SCKn SIn SOn Test points t WSKH t CYSK t DSSK Output data PD78P4916 0.8 V ...
Page 38
Serial Transfer Timing (Only SIO2) No busy processing t t WSKL WSKH SCK2 CYSK BUSY At active-high STRB Continue busy processing t t WSKL WSKH SCK2 CYSK BUSY At active-high STRB Terminate busy processing ...
Page 39
Super timer unit input timing 0 DFGIN, CFGIN, DPGIN, REEL0IN and REEL1IN logic level input 0 CSYNCIN logic level input Interrupt input timing 0.8 V NMI 0.8 V INTP0, INTP3 0.8 V INTP1, KEY0 - KEY4 ...
Page 40
Clock output timing t CLH 0 CLO 0 CLR 40 t CLF t CLL t CYCL PD78P4916 ...
Page 41
DC Programming Characteristics (T A Parameter Symbol Input voltage, high V IH Input voltage, low V IL Input leakage current I LIP Output voltage, high V OH1 V OH2 Output voltage, low V OL Output leakage current ...
Page 42
AC Programming Characteristics (T A PROM Write Operation Mode (Page Programming Mode) Parameter Symbol Address setup time CE set time Input data setup time Address hold time Input data hold time Output data hold time V setup time PP V ...
Page 43
PROM Write Mode (Byte Programming Mode) Parameter Symbol Address setup time CE set time Input data setup time Address hold time Input data hold time Output data hold time V setup time PP V setup time t DDP VDS Initial ...
Page 44
PROM Write Mode Timing (Page Programming Mode) Page data latch A2 - A16 AHL A0 Hi Data input VPS DDP t VDS V ...
Page 45
PROM Write Mode Timing (Byte Programming Mode A16 DDP t VPS V +1 DDP V DDP t VDS ...
Page 46
PACKAGE DRAWING 100 PIN PLASTIC QFP (14 20 100 1 G NOTE Each lead centerline is located within 0.15 mm (0.006 inch) of its true position (T.P.) at maximum material condition ...
Page 47
... For details about the recommended conditions, refer to the document “Semiconductor Device Mounting Technology Manual” (C10535E). For soldering methods and conditions other than those recommended below, contact your NEC sales representative. Table 7-1. Surface Mounting Type Soldering Conditions PD78P4916GF-3BA: 100-pin plastic QFP ( mm) ...
Page 48
... Assembler package common to the 78K/IV Series C compiler package common to the 78K/IV Series C compiler library source file common to the 78K/IV Series PROM programmer Programmer adapter connected to the PG-1500 Control program for PG-1500 In-circuit emulator common to the 78K/IV Series Break board common to the 78K/IV Series ...
Page 49
Notes 1. • PC-9800 series (for MS-DOS • IBM PC/AT and compatibles (for PC DOS TM • HP9000 series 700 (for HP-UX TM • SPARCstation (for SunOS TM TM • NEWS (NEWS-OS ) based 2. • PC-9800 series (for MS-DOS) ...
Page 50
APPENDIX B. SOCKET DRAWING AND RECOMMENDED FOOTPRINT * E EV-9200GF-100 1 No.1 pin index 50 Figure B-1. EV-9200GF-100 Drawing (For reference purpose only ITEM MILLIMETERS A 24 ...
Page 51
Figure B-2. Recommended EV-9200GF-100 Footprint (For reference purpose only ITEM MILLIMETERS A 26.3 B 21.6 0.65 ± 0.02 29=18.85 ± 0.05 C 0.026 0.65 ± 0.02 19=12.35 ± 0.05 D 0.026 E 15.6 F ...
Page 52
APPENDIX C. RELATED DOCUMENTS Document related to device PD784915 Subseries User’s Manual – Hardware PD784915 Subseries Special Function Register Table 78K/IV Series User’s Manual – Instructions 78K/IV Series Instruction Table 78K/IV Series Instruction Set 78K/IV Series Application Note – ...
Page 53
... Other documents Semiconductor Device Package Manual Semiconductor Device Mounting Technology Manual Quality Grades on NEC Semiconductor Devices NEC Semiconductor Device Reliability/Quality Control System Electrostatic Discharge (ESD) Test Guide to Quality Assurance for Semiconductor Devices Microcontroller-Related Product Guide - Third Party Products Caution The contents of the documents listed above are subject to change without prior notice to users. ...
Page 54
PD78P4916 ...
Page 55
... HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction connection is provided to the input pins possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry ...
Page 56
... The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited without governmental license, the need for which must be judged by the customer. The export or re-export of this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative. ...