UPD705100GJ-100-8EU NEC, UPD705100GJ-100-8EU Datasheet
UPD705100GJ-100-8EU
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UPD705100GJ-100-8EU Summary of contents
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... The PD705100 (also called V830 microcontroller for incorporation use, which belongs to the V830 family of the NEC original V800 series equipment, by integrating quick real-time responses, high-speed arithmetic/logical instructions, and functions suitable for individual applications. The following user’s manual describes details of the functions of the V830. Be sure to read it before designing an application system ...
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... A13 140 A12 141 A11 142 A10 143 V DD 144 V DD Caution Leave the IC1 pins open. Connect each IC2 pin to GND via a dedicated resistor. Connect each IC3 pin mm) via a dedicated resistor. DD PD705100 A1/BE3 ...
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... READY : Ready HLDRQ : Hold Request HLDAK : Hold Acknowledge SIZ16B : Bus Size 16 bit NMI : Non-Maskable Interrupt Request INT : Interrupt Request INTV0-INTV3 : Interrupt Level BCLK : Bus Clock CMODE : Clock Mode ASEL : Address Select RESET : Reset V : Power Supply DD GND : Ground IC1-IC3 : Internally Connected PD705100 3 ...
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BLOCK DIAGRAM INTV0-INTV3 INT Interrupt controller NMI V830 CPU core Barrel shifter System registers (11) RESET 32-bit adder (with sum-of-products function) General-purpose registers 32 bits 32 4 Instruction cache (4K) Instruction RAM (4K) Data cache (4K) Data RAM (4K) Write ...
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PIN FUNCTIONS ........................................................................................................................ 1.1 Pin Functions ................................................................................................................................. 2. ADDRESS SPACE ..................................................................................................................... 2.1 Memory Space ................................................................................................................................ 2.2 I/O Space ......................................................................................................................................... 3. 32-BIT BUS MODE ..................................................................................................................... 3.1 Relationship between External Accesses and Byte Enable Signals ..................................... 4. 16-BIT BUS MODE ..................................................................................................................... ...
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INSTRUCTIONS ......................................................................................................................... 11.1 Instruction Format ......................................................................................................................... 11.2 Instructions (Listed Alphabetically) ............................................................................................ 12. INTERRUPTS AND EXCEPTIONS ............................................................................................ 13. ELECTRICAL SPECIFICATIONS .............................................................................................. 14. PACKAGE DRAWING ................................................................................................................ 15. RECOMMENDED SOLDERING CONDITIONS ........................................................................ 6 PD705100 ...
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PIN FUNCTIONS 1.1 Pin Functions Pin name Input/output A2-A27 Tristate output Note A28-A31/CS0-CS3 D0-D31 Tristate input/output BE0, BE1 Tristate output BE2/BH BE3/A1 ST0-ST3 BCYST R/W READY Input HLDRQ HLDAK Output SIZ16B Input NMI INT INTV0-INTV3 BCLK CMODE ASEL RESET ...
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ADDRESS SPACE 2.1 Memory Space The V830 uses four chip select/address pins and 26 address bus pins to represent a 32-bit address. When the chip select function is used, a 256M-byte image space is created as three spaces and ...
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Figure 2-1. Memory Map FFFFFFFFH CS0 Built-in instruction RAM Cachable area C0000000H BFFFFFFFH Cachable area 80000000H 7FFFFFFFH CS0 Uncachable area CS3 CS2 CS1 40000000H 3FFFFFFFH Cachable area CS3 CS2 CS1 Built-in data RAM 00000000H Address space Chip select signal CS0 ...
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I/O Space The V830 represents the I/O space using 32 bits and supports a linear address space bytes. The 1G-byte area C0000000H-FFFFFFFFH is reserved as an internal I/O area. External I/O cannot be placed in ...
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The cache function is not effective within the I/O space. When the chip select function is used, the area is used as the 256M-byte image space represented by A2-A27. Figure 2-3. Image Space Used When Chip Select Function is Used ...
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The upper 1G-byte area (C0000000H-FFFFFFFFH) in the I/O space is reserved for internal I/O. To access internal I/O, the IN.W/OUT.W instructions (in words) must be used. When the internal I/O area is accessed, an external bus cycle is not activated. ...
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BUS MODE If the SIZ16B input, sampled at reset, is inactive, the external bus width becomes 32 bits (32-bit bus mode). In this mode, BE2/BH acts as BE2 and BE3/A1 acts as BE3. 3.1 Relationship between External Accesses ...
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... In 16-bit bus mode, D16-D31 are all set to the high-impedance state and BE0, BE1, BH, and A1 are output in a way suited to a 16-bit bus system. Connection to D16-D31 is not necessary. The SIZ16B input can be changed only when the V830 is reset. It cannot be changed at any other time. ...
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Lower halfword During read cycles, data is read from D0-D15. During write cycles, D0-D15 data read from the write buffer is output to D0-D15. Figure 4-2 shows the operation for lower halfword access. In this figure, A indicates the ...
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Ta, Tw1 state Write buffer Internal 16 operation 15 unit 4.2 Relationship between External Access and Byte Enable Signals In 16-bit bus mode, the BE3/A1 output acts as A1 and BE2/BH output acts as BH. External accesses are related to ...
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INTERRUPTS V830 interrupts include maskable interrupts, nonmaskable interrupts, and reset operations. 5.1 Maskable Interrupts Maskable interrupt requests are themselves denoted by INT, and their interrupt levels by INTV0 to INTV3. The following lists pin states and the corresponding interrupt ...
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Nonmaskable Interrupts The V830 samples an NMI at the rising edge of a bus clock pulse. When the NMI changes from the high to low level, an interrupt request is detected. Once a nonmaskable interrupt request has been detected, ...
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CLOCK CONTROLLER 6.1 Operation Modes The V830 supports two clock stop functions, namely, sleep mode and stop mode. Transition from one mode to another is made by executing special instructions HALT or STBY. The following lists the features of ...
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INTERNAL MEMORY The V830 has a 4K bytes 4 internal memory, consisting of four blocks (instruction cache, data cache, instruction RAM, and data RAM). The V830 allows any of these internal memory blocks to be accessed in one cycle. ...
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REGISTER SETS 8.1 Program Register Set The V830 has two types of register sets: general-purpose register sets which can be used by programmers, and system register sets which control the state of the V830. The width of all registers ...
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Program counter (PC) The program counter (PC register which holds the first address of the instruction being executed. Bit 0 of the program counter is fixed to 0, but is forcibly masked to 0 upon a branch ...
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System Register Set System registers are used to control the processor state, save exception/interruption information, and manage tasks. The V830 has eleven 32-bit system registers. These registers can be accessed using special instructions (LDSR and STSR instructions). #0 EIPC ...
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DATA SETS 9.1 Data Types The V830 supports three data types: byte (8 bits), halfword (16 bits), and word (32 bits). Data of these types must be aligned with byte, halfword, or word boundaries, respectively. Addressing is based on ...
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Integers In the V830, integers are represented by twos complements. They are expressed by bytes, halfwords, or words. Digit ordering for integers is as follows: Bit 0 is handled as the least significant bit, regardless of the data length. ...
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ADDRESS SPACE The V830 supports 4G-byte linear address spaces for both the memory space and I/O space. It assigns 32-bit addresses to the memory space. The maximum address is 2 Byte data aligned with each address is defined such ...
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Addressing Mode The V830 generates two types of addresses, as follows: • Instruction addresses (used by instructions involving branching) • Operand addresses (used by instructions which access data) 10.1.1 Instruction addresses The instruction address is determined by the contents ...
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Register addressing (via register) The contents of the general-purpose register (r0-r31) designated in the instruction are transferred to the program counter (PC). The JMP instruction uses this addressing. 31 Register m 31 10.1.2 Operand addresses (1) Register addressing In ...
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INSTRUCTIONS 11.1 Instruction Format The V830 uses two instruction formats: 16-bit and 32-bit. The 16-bit instructions include binary operation, control, and conditional branch instructions, while the 32-bit instructions include load/store and I/O operation instructions, instructions for handling 16 bits ...
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Medium-distance jump instruction format [FORMAT IV] This instruction format has a six-bit operation code field and a 26-bit displacement field (the lowest-order bit must be 0), giving a total length of 32 bits opcode (5) Three-operand ...
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Instructions (Listed Alphabetically) The instructions are listed below in alphabetic order of their mnemonics. Explanation of list format Operand(s) Format CY OV Instruction ADD reg1, reg2 Instruction Instruction mnemonic format (See Section 11.1.) Abbreviations of operands Abbreviation reg1 General-purpose ...
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Instruction Operand(s) Format ABC disp9 III ABE disp9 III ABGE disp9 III ABGT disp9 III ABH disp9 III ABL disp9 III ABLE disp9 III ABLT disp9 III ABN disp9 III ABNC disp9 III ABNE disp9 III ABNH disp9 III ABNL ...
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Instruction Operand(s) Format CY AND reg1, reg2 I - ANDI imm16 reg1, reg2 BC disp9 III - BDLD [reg1], [reg2] VII - BDST [reg2], [reg1] VII - BE disp9 III - BGE disp9 III - BGT disp9 III ...
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Instruction Operand(s) Format CMP reg1, reg2 I imm5, rag2 DIV reg1, reg2 I DIVU reg1, reg2 HALT IX IN.B disp16[reg1], VI reg2 IN.H disp16[reg1], VI reg2 IN.W disp16[reg1], VI reg2 ...
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Instruction Operand(s) Format CY JAL disp26 IV - JMP [reg1 disp26 IV - LD.B disp16[reg1 reg2 LD.H disp16[reg1 reg2 LD.W disp16[reg1 reg2 LDSR reg2, regID II MAC3 reg1, reg2, VIII - ...
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Instruction Operand(s) Format MACI imm16, V reg1, reg2 MACT3 reg1, reg2, VIII reg3 MAX3 reg1, reg2, VIII reg3 MIN3 reg1, reg2, VIII reg3 MOV reg1, reg2, I imm5, reg2 II MOVEA imm16, V reg1, reg2 MOVHI imm16, V reg1, reg2 ...
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Instruction Operand(s) Format CY MULI imm16 reg1, reg2 MULT3 reg1, reg2, VIII - reg3 MULU reg1, reg2 I - NOP III - NOT reg1, reg2 reg1, reg2 I - ORI imm16 reg1, reg2 ...
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Instruction Operand(s) Format SAR reg1 ,reg2 I imm5, reg2 II SATADD3 reg1, reg2, VIII reg3 SATSUB3 reg1, reg2, VIII reg3 SETF imm5, reg2 II SHL reg1, reg2 I imm5, reg2 II SHLD3 reg1, reg2, VIII reg3 ...
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Instruction Operand(s) Format CY SHR reg1, reg2 I imm5, reg2 II SHRD3 reg1, reg2, VIII - reg3 ST.B reg2 disp16[reg1] ST.H reg2 disp16[reg1] ST.W reg2 disp16[reg1] STBY IX - STSR regID,reg2 II - SUB ...
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Instruction Operand(s) Format XOR reg1,reg2 I XORI imm16, V reg1,reg2 Exclusive OR. The exclusive OR of reg2 and reg1 is taken and written into reg2 Exclusive OR. The exclusive OR of ...
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INTERRUPTS AND EXCEPTIONS Interrupts are events which occur independently of program execution. They are classified into maskable and nonmaskable interrupts. In contrast, exceptions are events which are directly related to program execution. Interrupts and exceptions do not differ greatly ...
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... Storage temperature T stg Cautions 1. Do not connect an output (or input/output) pin device directly to any other output (or input/output) pin of the same device, with the exception of the open-drain and open-collector pins. Also, do not connect the V Note, however, that these restrictions do not apply to the high-impedance pins of an external circuit, whose timing has been specifically designed to avoid output collision ...
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AC CHARACTERISTICS (T = –10 to +85˚ test input waveform (except BCLK test input waveform (BCLK test output waveform (except BCLK) Test load V830 output pin = ...
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Clock timing (a) When the internal operating frequency 100 MHz Parameter Symbol Clock period 1 Clock pulse high level width 2 Clock pulse low level width 3 Clock pulse rise time 4 Clock pulse fall time ...
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Reset timing (a) When the internal operating frequency 100 MHz Parameter Symbol RESET hold time 6 (relative to V VALID) DD Clock period (when reset) 7 Clock high level width (when reset) 8 Clock low level ...
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BCLK (input) RESET (input PD705100 12 11 ...
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Memory and I/O access timing (single transfer) (1/2) (a) When the internal operating frequency 100 MHz Parameter Symbol Address output delay 14 (relative to BCLK ) Address output hold time 15 (relative to BCLK ) CSn ...
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When the internal operating frequency 100 MHz Parameter Symbol Address output delay 14 (relative to BCLK ) Address output hold time 15 (relative to BCLK ) CSn output delay (relative to BCLK ) 16 CSn output ...
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Memory and I/O access timing (single transfer) (2/2) Ta BCLK (input) 14 Note 1 14 ST0-ST3 (output) 16 Note 2 CS0-CS3 (output) 18 BCYST (output) READY (input) D0-D31 (input/output) (read) 26 D0-D31 (input/output) (write) 24 D0-D31 (input/output) (write) Notes ...
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Memory access timing (burst transfer) (1/3) (a) When the internal operating frequency 100 MHz Parameter Symbol Address output delay 14 (relative to BCLK ) Address output hold time 15 (relative to BCLK ) CSn output delay ...
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When the internal operating frequency 100 MHz Parameter Symbol Address output delay t 14 (relative to BCLK ) Address output hold time t 15 (relative to BCLK ) CSn output delay (relative to BCLK ) t ...
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Memory access timing (burst transfer) (2/3) (c) 32-bit bus mode Ta Tb1 BCLK (input) 14 Note 1 16 Note 2 CS0-CS3 (output (output (output BCYST (output) READY (input) D0-D31 (input/output) (read) 26 D0-D31 ...
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Memory access timing (burst transfer) (3/3) (d) 16-bit bus mode Ta Tb1 BCLK (input) 14 A4-A27 (output), BE0-BE3 (output), R/W (output) 14 ST0-ST3 (output) 16 Note CS0-CS3 (output (output (output (output ...
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Interrupt timing (a) When the internal operating frequency 100 MHz Parameter Symbol NMI set time (relative to BCLK ) 28 NMI hold time (relative to BCLK ) 29 INT set time (relative to BCLK ) 30 ...
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Bus hold timing (1/2) (a) When the internal operating frequency 100 MHz Parameter Symbol CSn output delay (relative to BCLK ) 16 CSn output hold time 17 (relative to BCLK ) READY set time (relative to ...
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When the internal operating frequency 100 MHz Parameter Symbol CSn output delay (relative to BCLK ) 16 CSn output hold time 17 (relative to BCLK ) READY set time (relative to BCLK ) 20 READY hold ...
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Bus hold timing (2/2) Ta BCLK (input) 32 HLDRQ (input) HLDAK (output) Note 1 Note 2 CS0-CS3 (output) D0-D31 (input/output) (write) BCYST (output) READY (input) Notes 1. A2-A27 (output), BE0-BE3 (output), ST0-ST3 (output), R/W (output) 2. A28-A31 are output ...
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Halt acknowledge cycle (1/2) (a) When the internal operating frequency 100 MHz Parameter Symbol Address output delay 14 (relative to BCLK ) Address output hold time 15 (relative to BCLK ) CSn output delay (relative to ...
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When the internal operating frequency 100 MHz Parameter Symbol Address output delay t 14 (relative to BCLK ) Address output hold time t 15 (relative to BCLK ) CSn output delay (relative to BCLK ) t ...
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Halt acknowledge cycle (2/ BCLK (input) 14 Note BCYST (output) 16 Note 2 CS0-CS3 (output) ST0-ST3 (output) READY (input) D0-D31 (input/output) (read) 26 D0-D31 (input/output) (write) 24 D0-D31 (input/output) (write) Notes 1. A2-A27 (output), ...
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PACKAGE DRAWING 144 PIN PLASTIC LQFP (FINE PITCH) (20 20) 108 109 144 NOTE Each lead centerline is located within 0.10 mm (0.004 inch) of its true position (T.P.) at maximum material condition. A ...
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RECOMMENDED SOLDERING CONDITIONS The conditions listed below shall be met when soldering the PD705100. For details of the recommended soldering conditions, refer to our document Semiconductor Device Mounting Technology Manual (C10535E). Please consult with our sales offices in case ...
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... Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction connection is provided to the input pins possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS device behave differently than Bipolar or NMOS devices ...
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... Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: • Device availability • Ordering information • ...
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PD705100 65 ...
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... Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance ...