UPD98405GL-PMU NEC, UPD98405GL-PMU Datasheet
UPD98405GL-PMU
Related parts for UPD98405GL-PMU
UPD98405GL-PMU Summary of contents
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... QFP (0.5-mm fine pitch) (40 The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. S12689EJ2V0DS00 (2nd edition) ...
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SYSTEM CONFIGURATION EXAMPLE Control memory 2 ATM Interface Card Rx PMD Tx PD98405 Expansion ROM TM EEPROM PCI bus Data Sheet S12689EJ2V0DS00 PD98405 ATM network ...
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BLOCK DIAGRAM PMD PMD interface & Clock recovery & Clock synthesizer PCI interface Host system Data Sheet S12689EJ2V0DS00 PD98405 3 ...
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OUTLINE OF PINS 304-pin plastic QFP (0.5-mm fine pitch) (40 304 1 JTAG mm) PMD PHY device Control memory Data Sheet S12689EJ2V0DS00 PD98405 229 228 EEPROM 153 152 ...
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PIN NAME ABRT_B : Abort ACK64_B : Acknowledge 64-bit Transfer AD63-AD0 : Address/Data AGND : Ground for Analog Part ASEL_B : Slave Address Select ATTN_B : Attention AV : +3.3 V Power Supply for DD3 Analog Part BE3_B-BE0_B : Byte ...
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PIN CONFIGURATION 304-pin plastic QFP (0.5-mm fine pitch) (40 Generic No. PCI Mode No. PCI Mode Mode 1 GND GND 39 AD12 AD11 DD3 DD3 3 AD24 AD24 41 AD10 4 PCBE3_B BE3_B 42 AD9 5 ...
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Generic No. PCI Mode No. PCI Mode Mode 153 GND GND 191 CBE3_B 154 V V 192 CBE2_B DD3 DD3 155 CD5 CD5 193 CBE1_B 156 CD4 CD4 194 CBE0_B 157 CD3 CD3 195 CWE_B 158 CD2 CD2 196 COE_B ...
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PIN FUNCTIONS ............................................................................................................................... 1.1 PHY Layer Device Interface Signal .......................................................................................... 1.1.1 UTOPIA interface ........................................................................................................................... 1.1.2 PHY device control interface (external PHY mode, PHM of GMR register = 1) ............................. 1.2 Bus Interface Signals ................................................................................................................ 12 1.2.1 Generic bus interface ...
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... The PHY layer device interface signals are for an external PHY layer device. When using an internal PHY layer, open all the pins except the common pins. Even when the internal PHY layer is used, an external receive FIFO can be connected to the PD98405 via the UTOPIA interface. 1.1.1 UTOPIA interface Pin Name Pin No ...
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Pin Name Pin No. I/O EMPTY_B/ 248 I RCLAV (shared with RCIC) RCLK 244 O Tx7-Tx0 255-258, O 260-263 TSOC 250 O TENBL_B 251 O FULL_B/ 249 I TCLAV (shared with RCIT) TCLK 253 O 10 I/O Level Function TTL ...
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PHY device control interface (external PHY mode, PHM of GMR register = 1) Pin Name Pin No. I/O PHR/W_B 266 O (shared with PHYALM) PHOE_B 265 O PHCE_B 267 O (shared with SD) PHINT_B 268 I (shared with REFCLK) ...
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... The PD98405 supports a PCI bus interface or generic bus interface. Whether the PCI bus interface or generic bus interface supported is selected by the PCI_MODE signal. The PCI bus interface can be directly connected to a PCI bus. The generic bus interface can be connected to a general I/O bus with a few circuits. ...
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Pin Name Pin No. I/O SIZE2 63 O SIZE1 64 SIZE0 65 DR/W_B 60 O ATTN_B 294 O GNT_B 291 I RDY_B 23 I I/O Level Function TTL Burst size. These pins indicate the size of current DMA transfer. They ...
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Pin Name Pin No. I/O ABRT_B 27 I ERR_B 28 I SR/W_B 24 I SEL_B 21 I ASEL_B 22 I CLK 290 I RST_B 289 I INTR_B 288 O 14 I/O Level Function TTL Abort. This signal is used to ...
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... PCI bus interface signal (PCI_MODE pin: high level) The PD98405 has a 32-/64-bit PCI bus interface. This bus interface can be directly connected to a PCI bus. In addition, the PD98405 also has a serial EEPROM interface and an expansion ROM interface. <1> PCI bus interface signals Pin Name Pin No ...
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Pin Name Pin No. I/O STOP_B 27 I/O Sustained 3-state DEVSEL_B 24 I/O Sustained 3-state IDSEL 5 I Note REQ_B 294 O GNT_B 291 I PERR_B 28 I/O Sustained 3-state SERR_B 29 O INTR_B 288 O CLK 290 I RST_B ...
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PCI bus 64-bit expansion interface signals Open AD63 through AD32, PCBE7_B through PCBE4_B, and PAR64 when using the 32-bit PCI bus interface. Pin Name Pin No. I/O AD63-AD32 69-71, I/O 73-75, 79, 80, 3-state 82-85, 88-91, 94-97, 100-103, 106-109, ...
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... Serial EEPROM interface signals The PD98405 has a serial EEPROM interface supporting MICROWIRE EEPROM interface, the contents of the PCI configuration register can be loaded from an EEPROM connected. Remark It is recommended that National Semiconductor’s “NM93C46” be connected as the EEPROM. Pin Name Pin No. ...
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... Local port byte enable. These signals indicate the byte of the control port to be read or written. TTL Initialization disable. This signal is used to disable automatic initialization of the control memory during chip test. Directly connect INITD to GND during normal operation other than test. Data Sheet S12689EJ2V0DS00 PD98405 19 ...
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... PMD Interface Signals (internal PHY mode, PHM of GMR register = 0) The PMD interface is used to connect a module such as an optical transceiver/receiver. Pin Name Pin No. I/O RDIT 278 I RDIC 277 I RCIT (shared 249 I with FULL_B) RCIC (shared 248 I with EMPTY_B) REFCLK 268 I (shared with PHINT_B) ...
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... Connect this pin to ground when it is not used. TTL Boundary scan clock input. Connect this pin to ground when it is not used. TTL Boundary scan reset. Connect this pin to ground when it is not used. I/O Level Function TTL SAR system clock. This pin supplies a clock for a SAR block operation. ...
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Power and Ground Pin Name Pin No 20, 32, 44, 56, 67, 81, 93, DD5 105, 287, 299 V 2, 14, 26, 38, 50, 62, 72, 78, DD3 87, 99, 111, 125, 138, 151, 154, 175, 190, ...
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Pin Status during and after Reset Pin Name RENBL_B RCLK Tx7-Tx0 TSOC TENBL_B TCLK PHR/W_B (external PHY)/PHYALM (internal PHY) PHOE_B PHCE_B (external PHY)/SD (internal PHY) AD31-AD0 PCBE3_B-PCBE0_B (PCI)/BE3_B-BE0_B (Generic) PAR FRAME_B TRDY_B IRDY_B STOP_B DEVSEL_B REQ_B (PCI)/ATTN_B (Generic) PERR_B ...
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Pin Name CWE_B COE_B TDOT TDOC JDO Remark The internal PHY mode is set (PHM of GMR register = 0) after reset. 24 During Reset 1 1 Undefined Undefined Hi-Z Data Sheet S12689EJ2V0DS00 PD98405 (2/2) After Reset 1 1 Undefined ...
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ELECTRICAL SPECIFICATIONS * indicates changes from the Preliminary Data Sheet (document number: S12689E, 1st edition). Absolute Maximum Ratings Parameter Symbol Supply voltage V Input/output voltage Ambient operating frequency Storage temperature Notes Clamping diode-dedicated power supply DD5 ...
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DC Characteristics ( +70° Parameter Symbol High-level output voltage V OH1 V OH2 V OH3 V OH4 Low-level output voltage V OL1 V OL2 V OL3 V OL4 V OL5 Supply current I DD Input ...
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Capacitance (T = +25° Parameter Symbol Input capacitance C IN CLK input capacitance C CLK IDSEL input capacitance C IDSEL Output capacitance C OUT I/O capacitance C I/O Internal pull-down resistor ( ...
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AC Characteristics ( +70° CLK input (BUS interface clock - CLK pin) Parameter Symbol CLK cycle time t CYCLK CLK high-level width t CLKH CLK low-level width t CLKL CLK slew rate slew 2.0 V ...
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Data Sheet S12689EJ2V0DS00 PD98405 29 ...
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PCI Bus Interface Bus master read Parameter Symbol CLK FRAME_B, REQ64_B valid t time CLK FRAME_B, REQ64_B float t DFRAMEF time CLK AD (Address) valid time CLK AD (Address) float time t AD (Data) setup time AD (Data) hold time ...
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Bus master read CLK t DFRAME FRAME_B REQ64_B t DADDRF t DADDR AD31-AD0 (Address) AD63-AD32 t DPCBE PCBE3_B- PCBE0_B t DPCBE PCBE7_B- PCBE4_B t DIRDY IRDY_B TRDY_B DEVSEL_B ACK64_B t DPAR PAR PAR64 PERR_B CLK STOP_B t DFRAMEF t t ...
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Bus master write Parameter Symbol CLK FRAME_B, REQ64_B valid t time CLK FRAME_B, REQ64_B float t DFRAMEF time CLK AD (Address) valid time CLK Data valid time CLK Data float time t CLK PCBE_B valid time CLK PCBE_B float time ...
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Bus master write CLK t DFRAME FRAME_B REQ64_B t DADDR AD31-AD0 (Address) AD63-AD32 t DPCBE PCBE3_B- PCBE0_B PCBE7_B- PCBE4_B t DIRDY IRDY_B TRDY_B DEVSEL_B ACK64_B t DPAR PAR PAR64 PERR_B CLK STOP_B t DFRAMF t DDATAF t DDATA (Data) t ...
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Target read Parameter Symbol FRAME_B setup time t FRAME_B hold time t AD (Address) setup time AD (Address) hold time t CLK AD (Data) valid time CLK AD (Data) float time t PCBE_B setup time PCBE_B hold time IRDY_B setup ...
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Target read CLK t HFRAME t SFRAME FRAME_B t t SADDR HADDR AD31-AD0 (Address SPCBE HPCBE PCBE3_B- PCBE0_B t SIRDY IRDY_B TRDY_B t DEVSEL_B t SPAR PAR PERR_B CLK STOP_B t DDATAF t DDATA (Data) t HIRDY t ...
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Target write Parameter Symbol FRAME_B setup time t FRAME_B hold time t AD (Address) setup time AD (Address) hold time t AD (Data) setup time AD (Data) hold time PCBE_B setup time PCBE_B hold time IRDY_B setup time IRDY_B hold ...
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Target write CLK t HFRAME t SFRAME FRAME_B t HADDR t SADDR AD31-AD0 (Address SPCBE HPCBE PCBE3_B- PCBE0_B t SIRDY IRDY_B TRDY_B t DEVSEL_B t SPAR PAR PERR_B CLK STOP_B t SDATA t HDATA (Data) t HIRDY t ...
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Bus arbitration Parameter Symbol CLK REQ_B valid time GNT_B setup time GNT_B hold time Bus arbitration CLK t DREQ REQ_B GNT_B 38 Condition MIN. t DREQ t SGNT t HGNT t t SGNT HGNT Data Sheet S12689EJ2V0DS00 PD98405 TYP. MAX. ...
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Configuration read Parameter Symbol FRAME_B setup time t FRAME_B hold time t AD (Address) setup time AD (Address) hold time t CLK AD (Data) valid time CLK AD (Data) float time t PCBE_B setup time PCBE_B hold time IDSEL setup ...
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Configuration read CLK t HFRAME t SFRAME FRAME_B t t SADDR HADDR AD31-AD0 (Address SPCBE HPCBE PCBE3_B- PCBE0_B t t SIDSEL HIDSEL IDSEL t SIRDY IRDY_B TRDY_B DEVSEL_B t SPAR PAR PERR_B 40 t DDATAF t DDATA (Data) ...
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EEPROM interface Parameter Symbol E2PCLK high-level width t WE2PCKLH E2PCLK low-level width t WE2PCLKL E2PCLK E2PCS valid time t E2PCS E2PCLK t E2PCLK E2PDO valid time t E2PDI E2PCLK setup time t E2PCLK E2PDI hold time t E2PCS E2PDI (Status) ...
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Expansion ROM interface Parameter Symbol ROMOE_B ROMD valid time t DROMOE ROMCS_B ROMD valid time t DROMCS ROMA valid time ROMD valid t ROMACC time ROMOE_B ROMD float time t HROMOE ROMCS_B ROMD float time t HROMCS ROMA invalid time ...
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Generic bus interface Slave write access Parameter Symbol ASEL_B setup time t SASEL ASEL_B hold time t HASEL SEL_B setup time t SSEL SEL_B hold time t HSEL Address setup time t SDADD Address hold time t HDADD Data setup ...
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Slave read access Parameter Symbol ASEL_B setup time t SASEL ASEL_B hold time t HASEL SEL_B setup time t SSEL SEL_B hold time t HSEL Address setup time t SDADD Address hold time t HDADD CLK data delay time t ...
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DMA write access Parameter Symbol CLK ATTN_B delay time t DATTN GNT_B setup time t SGNT GNT_B hold time t HGNT CLK DR/W_B delay time t DDRW CLK SIZE delay time t DSIZE CLK address delay time t DSADD CLK ...
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DMA write access (Example: 2-word burst) CLK t DATTN ATTN_B t SGNT GNT_B t DDRW DR/W_B t DSIZE SIZE2-SIZE0 t DSADD AD31-AD0 BE3_B-BE0_B RDY_B (Normal mode) RDY_B (Early mode) PAR3-PAR0 t HGNT t FSADD Data 0 (output) Address (output) t ...
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DMA read access Parameter Symbol CLK ATTN_B delay time t DATTN GNT_B setup time t SGNT GNT_B hold time t HGNT CLK DR/W_B delay time t DDRW CLK SIZE delay time t DSIZE CLK address delay time t DSADD CLK ...
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DMA read access (Example: 2-word burst) CLK t DATTN ATTN_B t SGNT GNT_B t DDRW DR/W_B t DSIZE SIZE2-SIZE0 t DSADD AD31-AD0 BE3_B-BE0_B RDY_B (Normal mode) RDY_B (Early mode) PAR3-PAR0 t HGNT t t SSDAT FSADD Data 0 Address (output) ...
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ABRT_B, ERR_B, and OE_B pins Parameter Symbol ABRT_B setup time t SABRT ABRT_B hold time t HABRT ERR_B setup time t SERR ERR_B hold time t HERR OE_B AD/PAR output t DADOE determination time OE_B AD/PAR high-impedance t FADOE determination ...
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UTOPIA interface (external PHY mode) Transmission operation Parameter Symbol SCLK TCLK delay time t DTCLK TCLK Tx delay time t TCLK TSOC delay time t DTSOC TCLK TENBL_B delay time t DTEN FULL_B setup time t SFULL FULL_B hold time ...
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UTOPIA interface (1) Transmission timing TCLK t DTX Tx7-Tx0 TSOC t t DTSOC DTSOC TENBL_B t SFULL FULL_B H1-H4: ATM header P1-P9: Payload data ‘00H’ P1 Invalid DTEN t DTEN t HFULL P4 ...
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UTOPIA interface (2) Reception timing RCLK t t SRX HRX Rx7-Rx0 RSOC t HRSOC t SRSOC RENBL_B t SEMPT EMPTY_B H1-H4: ATM header P1-P7: Payload data Invalid DREN t HEMPT Invalid P3 ...
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Control memory access Write Parameter Symbol CA CWE_B setup time t SCWE CBE_B CWE_B setup time t SCWE2 CWE_B low-level width t CWEL CWE_B CD float time t FCD CWE_B COE_B delay time t DCOE CA hold time (vs CWE_B ...
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Read Parameter Symbol Permissible CD delay time t DCDCB (vs CBE_B ) Permissible CD delay time (vs CA) t DCDCA Permissible CD delay time t DCDCO (vs COE_B ) CD hold time (vs CBE_B ) t HCDCB CD hold time ...
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Read timing SCLK CBE3_B- CBE0_B CA18-CA0 “H” CWE_B COE_B CD31-CD0 CPAR3-CPAR0 t DCDCB t DCDCA t DCDCO (Input) (Input) t DCPCO t DCPCA t DCPCB Data Sheet S12689EJ2V0DS00 PD98405 t HCDCB t HCDCA t HCDCO t HCPCO t HCPCA t ...
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PHY status access Write Parameter Symbol SCLK CA delay time t DPCA SCLK PHRW_B delay time t DPHRW SCLK PHCE_B delay time t DPHCE SCLK CD delay time t DPCD PHCE_B CD float time t FPCD Write timing 1 clock ...
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Read timing 1 clock 6 clocks SCLK t DPCA CA18-CA0 t DPHRW PHRW_B t DPHCE PHCE_B PHOE_B CD31-CD0 5 clocks 4 clocks t DPCA t DPHOE t SPCD (Input) t DPHCE t DPHOE t HPOECD ...
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PMD serial interface (internal PHY mode) Parameter Symbol REFCLK cycle time t CYRF REFCLK high-level width t WRFH REFCLK low-level width t WRFL REFCLK 58 Condition MIN. –20 ppm 0.4 t CYRF 0.4 t CYRF t t WRFH WRFL t ...
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Others Parameter Symbol SEL_B recovery time t RVSEL SEL_B GNT_B recovery time t RVSM RDY_B SEL_B recovery time t RVMS RST_B input pulse width t RSTL RST_B SEL_B recovery time t RSTSL Others timing CLK SEL_B GNT_B RDY_B t RSTL ...
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PACKAGE DRAWING 304 PIN PLASTIC QFP (FINE PITCH) (40x40) 228 229 304 NOTE Each lead centerline is located within 0. its true position (T.P.) at maximum material condition 153 ...
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... Solder this product under the following recommended conditions. For details of the recommended soldering conditions, refer to information document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and conditions other than those recommended, consult NEC. Surface-mount type • PD98405GL-PMU: 304-pin plastic QFP (0.5-mm fine pitch) (40 ...
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Data Sheet S12689EJ2V0DS00 PD98405 ...
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Data Sheet S12689EJ2V0DS00 PD98405 63 ...
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... Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance ...