UPD31172F1-48-FN NEC, UPD31172F1-48-FN Datasheet
UPD31172F1-48-FN
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UPD31172F1-48-FN Summary of contents
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... Peripheral devices for PCs, etc. The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information. Document No. U14388EJ2V0DS00 (2nd edition) ...
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ORDERING INFORMATION Part Number PD31172F1-48-FN 208-pin plastic FBGA (15 PIN CONFIGURATION 208-pin plastic FBGA (15 15) PD31172F1-48-FN Bottom View Package Internal Maximum Operating Frequency 15 ...
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Symbol Name Symbol A1 GND C2 A2 AUTOFEED INIT IOCHRDY C6 A6 AD19 C7 A7 AD20 C8 A8 AD21 C9 A9 AD22 C10 A10 AD23 C11 A11 AD24 C12 Note 1 A12 Reserved ...
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Symbol Name Symbol P1 HOLDRQ BUSAK0 BUSRQ1 GND R4 P5 DATA31 R5 P6 DATA30 R6 P7 DATA29 R7 P8 DATA28 P10 DATA27 R10 P11 DATA26 R11 P12 DATA25 R12 ...
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PIN IDENTIFICATION ACK#: Acknowledge AD (0:24): Address Bus ARBCLKSEL: Arbitration Clock Select AUTOFEED#: Autofeed BUSAK (0:1)#: Bus Acknowledge BUSCLK: System Bus Clock BUSRQ (0:1)#: Bus Request BUSY: Busy CD (0:7): Centronics Data CKE: Clock Enable CLKOUT48M: Clock Out of 48 ...
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... INTERNAL BLOCK DIAGRAM AND EXTERNAL BLOCK CONNECTION EXAMPLE 48 MHz SDRAM V 4121 4172 RC DRAM controller USB host PCI bus controller controller (OpenHCI 1.0) IEEE1284 parallel controller 16550 serial controller PS/2 controller PWM controller PCS (6 bits) GPIO (24 bits) PMU ICU Data Sheet U14388EJ2V0DS00 PD31172 2 ports ...
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... PIN FUNCTIONS................................................................................................................................... 8 1.1 Pin Function List ....................................................................................................................................... 8 1.2 Special Status Pins ................................................................................................................................. 11 1.3 External Processing of Pins and Drive Capacity.................................................................................. 13 1.4 Recommended Connection of Unused Pins......................................................................................... 15 2. ELECTRICAL SPECIFICATIONS...................................................................................................... 16 3. PACKAGE DRAWING ....................................................................................................................... 38 4. RECOMMENDED SOLDERING CONDITIONS................................................................................ 39 CONTENTS Data Sheet U14388EJ2V0DS00 PD31172 7 ...
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PIN FUNCTIONS 1.1 Pin Function List (1) System bus interface signals Signal Name I/O SCLK I/O This is the SDRAM operating clock. AD (0:24) I/O These form a 25-bit address bus. DATA (0:31) I/O These form a 32-bit data ...
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USB Interface Signals Signal Name I/O DP (1:2) I/O This is the positive data signal. DN (1:2) I/O This is the negative data signal. PPON (1:2) Output This is the USB route-hub-port power supply control signal. OCI (1:2) Input ...
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... XIN48M Input This is the 48 MHz oscillator input pin. Connect to one side of a crystal resonator. XOUT48M Output This is the 48 MHz oscillator output pin. Connect to the other side of the crystal resonator. CLKOUT48M Output This is the 48 MHz clock output for the FIR of the V 10 ...
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Special Status Pins Signal Name SCLK AD (0:24) DATA (0:31) LCDCS# RD# WR# LCDRDY ROMCS (2:3)# CKE UUCAS# ULCAS# MRAS (0:1)# UCAS# LCAS# IOR# IOW# RESET IOCS16# IOCHRDY HOLDRQ# HOLDAK# SRAS# SCAS# BUSRQ (0:1)# BUSAK (0:1)# INTRP IRQ USBINT# ...
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Signal Name SMI# USBRST# CD (0:7) STROBE# ACK# BUSY PE SELECT AUTOFEED# SELECTIN# ERROR# INIT# DIR1284 RXD CTS# DSR# TXD RTS# DTR# DCD# RI# PS2CLK PS2DATA GPIO (0:23) EXCS (0:5)# LCDBAK CLKOUT48M Remark 0: Low level, 1: High level, Hi-Z: ...
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External Processing of Pins and Drive Capacity When using the V 4172, process the pins externally, as shown in the table below. RC Signal Name External Processing SCLK AD (0:24) DATA (0:31) LCDCS# Pull up RD# Pull up WR# ...
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Signal Name External Processing PPON (1:2) OCI (1:2) IEN WAKE SMI# USBRST# CD (0:7) STROBE# Pull up ACK# Pull up BUSY Pull down PE Pull down SELECT Pull down AUTOFEED# Pull up SELECTIN# Pull up ERROR# Pull up INIT# Pull ...
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... Leave open IRQ Leave open USBINT# Leave open PS2INT Leave open BUSCLK Pull up ARBCLKSEL Pull down DP (1:2) Pull down DN (1:2) Pull down Remark Pins with no particular specification ( ) cannot be left unconnected. Signal Name PPON (1:2) OCI (1:2) IEN WAKE SMI# USBRST# CD (0:7) STROBE# ACK# BUSY PE SELECT AUTOFEED# ...
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ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings ( Parameter Symbol Power supply voltage V DD Input voltage V I Output voltage V O Operating ambient temperature T A Storage temperature T stg Cautions 1. Do not simultaneously ...
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... Remark Refer to the USB specification, revision 1.0, for details. = 3.3 0 Conditions = GND ARBCLKSEL pin GND DD Conditions = 15 k (connected to GND) = 1.5 k (connected < 200 mV Data Sheet U14388EJ2V0DS00 PD31172 MIN. MAX. Unit 2.4 V 0.4 V 2.4 V 0.4 V 2.4 V 0 ...
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AC Characteristics ( + test input waveform V DD All output pins test output test points V DD All output pins 3.3 0 1.4 ...
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Load Conditions (a) SCLK, AD (0:24), DATA (0:31), RD#, WR#, ROMCS (2:3)#, CLK#, UUCAS#, ULCAS#, ULCAS#, MRAS (0:1)#, UCAS#, LCAS#, SRAS#, SCAS# SCLK, AD (0:24), DATA (0:31), RD#, WR#, ROMCS (2:3)#, CLK#, UUCAS#, ULCAS#, MRAS (0:1)#, UCAS#, LCAS#, SRAS#, SCAS# ...
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Clock parameters Parameter Symbol XIN48M clock frequency f CLK (2) Reset parameters Parameter Symbol RESET signal high-level width t RST USBRST# signal low-level width t USBRST (3) SDRAM interface parameters Parameter Symbol SCLK cycle t SCLK SCLK high-level width ...
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System bus interface parameters (a) Access to I/O area Parameter Command signal low-level width Address setup time (to command signal) Address hold time (from command signal) IOCS16# valid delay time IOCS16# floating delay time Data output hold time Data ...
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Access to LCD area Parameter Command signal low-level width Address setup time (to command signal) Address hold time (from command signal) LCDRDY valid delay time LCDRDY set delay time LCDRDY floating delay time Data output hold time Data output ...
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When accessing the configuration register of the PCI host controller AD (24:0) (input) LCDCS# (input) t AVCL RD#/WR# (input) LCDRDY Hi-Z (output) DATA (31:0) (input) Hi-Z DATA (31:0) (output) Data Sheet U14388EJ2V0DS00 t CHAV t CLCH ...
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GPIO parameters Parameter GPIO (23:0) output delay time GPIO (23:0) interrupt request generation time GPIO (23:0) interrupt request clear time (a) In output mode IOW# (input) GPIO (23:0) (output) (b) In input mode GPIO (23:0) (input) IRQ (output) (level ...
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PCS (Programmable Chip Select) parameters Parameter Symbol EXCS output delay time (24:0) (I/O) EXCS (5:0)# (output) (7) PWM (Pulse Width Modulation) parameters Parameter Symbol LCDBAK output delay time t LO IOW# (input) LCDBAK Note (output) Note ...
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PS/2 parameters Parameter PS2CLK clock high-level width PS2CLK clock low-level width PS2CLK output delay time Transmission start time Transmit data output delay time Receive data setup time Receive data hold time Receive disable setup time Remark T = 125 ...
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Parameter Transmit clock division ratio Transmit clock rising edge delay time (from CLK Transmit clock falling edge delay time (from CLK Transmit clock pulse low-level width Transmit clock pulse high-level width Interrupt cancellation time (from ...
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Serial BAUDOUT timing CLK (internal, 1.8462 MHz) t BHD BAUDOUTB (1 cycle) (internal) t BLD BAUDOUTB (2 cycles) (internal) t BLD BAUDOUTB (3 cycles) (internal) t BLD BAUDOUTB (N cycles, N > 3) (internal) (b) Serial receive timing RCLK ...
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Serial transmission timing RXD (input) t IRS Note INTRP t (output) HR IOW# (input) (writing to THR register) IOR# (input) (reading IIR register) Note Dependant on whether the transmit buffer is empty. At this time, bit 1 of the ...
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IEEE1284-compliant parallel interface parameters (a) Parallel port control signal output Parameter Parallel interface internal clock frequency CD (7:0) output delay time (writing to DATA register) INIT#, STROBE#, AUTOFEED#, SELECTIN# setup time DIR1284 setup time Remark T: Parallel interface internal ...
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During ECP normal-direction transfer Parameter CD (7:0), AUTOFEED# setup time BUSY response time (from STROBE# ) STROBE# response time BUSY response time (from STROBE (7:0) hold time Note STROBE# setup time Note When the FIFO buffer is ...
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Write timing in EPP1.9 mode Parameter IOCHRDY setup time CD (7:0) output delay time STROBE# setup time, DIR1284 cancellation time (from IOW# ) STROBE# setup time, DIR1284 cancellation time (from BUSY ) SELECTIN#, AUTOFEED# setup time (from STROBE# , ...
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Read timing in EPP1.9 mode Parameter IOCHRDY setup time STROBE# setup time, DIR1284 cancellation time (from IOR# ) STROBE# setup time, DIR1284 cancellation time (from BUSY ) SELECTIN#, AUTOFEED# setup time (from IOR# ) SELECTIN#, AUTOFEED# setup time (from ...
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Write timing in EPP1.7 mode Parameter CD (7:0) output delay time STROBE# setup time SELECTIN#, AUTOFEED# setup time IOCHRDY setup time Timeout generation time IOCHRDY cancellation time SELECTIN#, AUTOFEED# cancellation time STROBE# cancellation time CD (7:0) hold time Remark ...
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Read timing in EPP1.7 mode Parameter DIR1284 setup time SELECTIN#, AUTOFEED# setup time IOCHRDY setup time Timeout generation time IOCHRDY cancellation time SELECTIN#, AUTOFEED# cancellation time CD (7:0) hold time DIR1284 cancellation time Remark T: Parallel interface internal clock ...
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Interrupt request timing Parameter Interrupt request setup time Interrupt request generation time (from ACK# , ERROR# ) Interrupt request cancellation time (from IOW# ) Note Interrupt request cancellation time (from IOR# ) Interrupt request generation time (from IOW# ) ...
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USB interface Applicable to the DP (2:1) and DN (2:1) pins. Refer to the USB specification, revision 1.0, for details. Parameter Full-speed Rise time mode Fall time matching R F Differential output signal crossover point Low-speed ...
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PACKAGE DRAWING 208-PIN PLASTIC FBGA (15x15) OUTLINE DRAWINGS D D1 INDEX MARK 4 – R0 208 – ...
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... The PD31172 should be soldered and mounted under the following recommended conditions. For the details of the recommended soldering conditions, refer to the document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and conditions other than those recommended below, contact your NEC sales representative. Table 4-1. Surface Mounting Type Soldering Conditions ...
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Data Sheet U14388EJ2V0DS00 PD31172 ...
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Data Sheet U14388EJ2V0DS00 PD31172 41 ...
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... HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction connection is provided to the input pins possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry ...
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... Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, pIease contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: Device availability • Ordering information • ...
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... Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance ...