UPD75P3116GC-AB8 NEC, UPD75P3116GC-AB8 Datasheet
UPD75P3116GC-AB8
Related parts for UPD75P3116GC-AB8
UPD75P3116GC-AB8 Summary of contents
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... PD75P3116GC-AB8 64-pin plastic QFP ( mm, 0.8-mm pitch) PD75P3116GK-8A8 64-pin plastic QFP ( mm, 0.65-mm pitch) Caution This device does not provide an internal pull-up resistor connection function by means of mask option. The information in this document is subject to change without notice. Document No. U11369EJ2V0DS00 (2nd edition) Date Published March 1997 N ...
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... Internal pull-up resistor connection can be specified by software Internal pull-up resistor connection can be specified by software: 12 Shared by segment pin 13-V withstand voltage 32 • Segment number selection : 16/20/24 segments (Switchable to CMOS I/O ports in a batch of 4 pins, max. 8 pins) • ...
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... Port Pins ................................................................................................................................................... 3.2 Non-port Pins ........................................................................................................................................... 3.3 Equivalent Circuits for Pins .................................................................................................................... 10 3.4 Recommended Connection of Unused Pins ......................................................................................... AND Mk II MODE SELECTION FUNCTION ............................................................................. 13 4.1 Differences between Mk I Mode and Mk II Mode ................................................................................... 13 4.2 Setting of Stack Bank Selection (SBS) Register ................................................................................... 14 5. DIFFERENCES BETWEEN PD75P3116 AND PD753104, 753106, AND 753108 ...................... 15 6 ...
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... P33/MD3 8 Vss 9 P50/D4 10 P51/D5 11 P52/D6 12 P53/D7 13 P60/KR0/D0 14 P61/KR1/D1 15 P62/KR2/ Note Always connect the V PP PIN IDENTIFICATIONS P00-P03 : Port0 P10-P13 : Port1 P20-P23 : Port2 P30-P33 : Port3 P50-P53 : Port5 P60-P63 : Port6 P80-P83 : Port8 P90-P93 : Port9 KR0-KR3 ...
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BLOCK DIAGRAM WATCH BUZ/P23 TIMER INTW f LCD PROGRAM BASIC COUNTER (14) INTERVAL TIMER/ WATCHDOG TIMER INTBT 8-BIT TI0/P13 TIMER/EVENT PTO0/P20 COUNTER #0 INTT0 TOUT0 INTT1 TI1/TI2/ 8-BIT CASCADED P12/INT2 PROGRAM TIMER/EVENT 16-BIT PTO1/P21 COUNTER #1 TIMER/ EVENT PTO2/ ...
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... Low-level input leakage current increases when input instructions or bit manipulation instructions are executed. 6 Function 4-bit input port (PORT0) P01 to P03 are 3-bit pins for which connection of an internal pull-up resistor can be specified by software. 4-bit input port (PORT1) Connection of an internal pull-up resistor can be specified by software in 4-bit units ...
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... S16 Notes 1. Circuit types enclosed in brackets indicate Schmitt trigger input. 2. Low-level leak current increases when an input instruction or a bit manipulation instruction is performed not connect an internal pull-up resistor by software when used as the segment signal output. Function Programmable 4-bit I/O port (PORT6) Input and output in single-bit units can be specified. ...
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... DD Vss — — Notes 1. Circuit types enclosed in brackets indicate Schmitt trigger input. 2. The V pin does not operate correctly when it is not connected to the Function External event pulse input to timer/event counter Timer/event counter output Clock output Frequency output (for buzzer or system clock trimming) ...
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... LCDCL I/O P30/MD0 Note 3 SYNC I/O P31/MD1 Notes 1. The V pin does not operate normally not connected with The shown below are selected as the input source for the display outputs. LCX S0 to S23 COM0 to COM2: V LC1 3. When the split resistor is incorporated When the split resistor is not incorporated : High impedance 4 ...
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Equivalent Circuits for Pins The equivalent circuits for the PD75P3116’s pins are shown in abbreviated form below. TYPE P-ch IN N-ch CMOS standard input buffer TYPE B IN Schmitt trigger input with hysteresis characteristics. TYPE B-C ...
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TYPE F-B P.U.R. enable Output V DD disable (P) P-ch Data Output N-ch disable Output disable (N) P.U.R. : Pull-Up Resistor TYPE G-A P-ch V LC0 N-ch P-ch V LC1 N-ch P-ch SEG data P-ch V LC2 N-ch N-ch TYPE ...
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... DD Output status : Leave open Leave open Input status : Individually connect to Vss or V through a resistor DD Output status : Leave open Connect to Vss Connect to Vss only when neither LC0 LC1 V is used. In other cases, leave open. LC2 Connect to Vss Leave open ...
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Mk I AND Mk II MODE SELECTION FUNCTION Setting a stack bank selection (SBS) register for the PD75P3116 enables the program memory to be switched between the Mk I mode and Mk II mode. This function is applicable when ...
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Setting of Stack Bank Selection (SBS) Register Use the stack bank selection register to switch between the Mk I mode and Mk II mode. Figure 4-1 shows the format of the stack bank selection register. The stack bank selection ...
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DIFFERENCES BETWEEN PD75P3116 AND PD753104, 753106, 753108 The PD75P3116 replaces the internal mask ROM in the PD753104, 753106, and 753108 with a one-time PROM and features expanded ROM capacity. The PD75P3116’ mode supports the Mk I mode ...
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MEMORY CONFIGURATION 0000H MBE RBE Internal reset start address (upper 6 bits) Internal reset start address (lower 8 bits) 0002H MBE RBE INTBT/INT4 start address (upper 6 bits) INTBT/INT4 start address (lower 8 bits) 0004H MBE ...
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General-purpose register area Note Stack area Data area static RAM (512 x 4) Display data memory Peripheral hardware area Note Memory bank can be selected as the stack area. Figure 6-2. Data Memory Map Data memory 000H ...
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INSTRUCTION SET (1) Representation and coding formats for operands In the instruction’s operand area, use the following coding format to describe operands corresponding to the instruction’s operand representations (for further description, refer to the RA75X Assembler Package User’s Manual ...
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Operation legend register; 4-bit accumulator register register register register register register register XA : Register ...
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Description of symbols used in addressing area MB = MBE • MBS *1 MBS = MBE = (000H to 07FH (F80H to FFFH) *3 ...
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Instruction Mnemonic Operand group Transfer MOV A, #n4 reg1, #n4 XA, #n8 HL, #n8 rp2, #n8 A, @HL A, @HL+ A, @HL– A, @rpa1 XA, @HL @HL, A @HL mem XA, mem mem, A mem reg ...
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Instruction Mnemonic Operand group Bit transfer MOV1 CY, fmem.bit CY, pmem.@L CY, @H+mem.bit fmem.bit, CY pmem.@L, CY @H+mem.bit, CY Arithmetic ADDS A, #n4 XA, #n8 A, @HL XA, rp’ rp’1, XA ADDC A, @HL XA, rp’ rp’1, XA SUBS A, ...
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Instruction Mnemonic Operand group Comparison SKE reg, #n4 @HL, #n4 A, @HL XA, @HL A, reg XA, rp’ Carry flag SET1 CY manipulation CLR1 CY SKT CY NOT1 CY Memory bit SET1 mem.bit manipulation fmem.bit pmem.@L @H+mem.bit CLR1 mem.bit fmem.bit ...
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Instruction Mnemonic Operand group Branch BR Note 1 addr addr1 !addr $addr $addr1 PCDE PCXA BCDE BCXA BRA Note 1 !addr1 BRCB !caddr Notes 1. The portion in a double box can be supported only in the Mk II mode. ...
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Instruction Mnemonic Operand group Subroutine CALLA Note !addr1 stack control CALL Note !addr CALLF Note !faddr RET Note RETS Note RETI Note Note The portion in a double box can be supported only in the Mk II mode. Other portions ...
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Instruction Mnemonic Operand group Subroutine PUSH rp stack control BS POP rp BS Interrupt EI control IEXXX DI IEXXX I/O IN Note 1 A, PORTn XA, PORTn Note 1 OUT PORTn, A PORTn, XA CPU control HALT STOP NOP Special ...
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... D4/P50 to D7/P53 (upper 4 bits Caution Pins not used for program memory write/verify should be connected to Vss. 8.1 Operation Modes for Program Memory Write/Verify When + applied to the V pin and +12 the V DD mode. The following operation modes can be specified by setting pins MD0 to MD3 as shown below. ...
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Program Memory Write Procedure Program memory can be written at high speed using the following procedure. (1) Pull down unused pins to Vss through resistors. Set the X1 pin low. (2) Supply the V and V ...
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Program Memory Read Procedure The PD75P3116 can read program memory contents using the following procedure. (1) Pull down unused pins to V through resistors. Set the X1 pin low. SS (2) Supply the V and V ...
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... One-time PROM Screening Due to its structure, the one-time PROM cannot be fully tested before shipment by NEC. Therefore, NEC recommends that after the required data is written and the PROM is stored under the temperature and time conditions shown below, the PROM should be verified via a screening. ...
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ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS (T A Parameter Symbol Power supply voltage V DD PROM power supply V PP voltage Input voltage V Except port Port 5 (N-ch open drain) I2 Output voltage V O Output ...
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... Therefore, set PCC to a value other than 0011. 3. The oscillation stabilization time is necessary for oscillation to stabilize after applying V the STOP mode. Caution When using the main system clock oscillator, wiring in the area enclosed with the dotted line should be carried out as follows to avoid an adverse effect from wiring capacitance. • ...
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... Notes 1. Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time. 2. The oscillation stabilization time is necessary for oscillation to stabilize after applying V Caution When using the subsystem clock oscillator, wiring in the area enclosed with the dotted line should be carried out as follows to avoid an adverse effect from wiring capacitance. ...
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DC CHARACTERISTICS (T = –40 to +85˚ Parameter Symbol Output current low I Per pin OL Total of all pins Input voltage high V Ports and 9 IH1 V Ports RESET IH2 ...
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DC CHARACTERISTICS (T = –40 to +85˚ Parameter Symbol LCD drive voltage V VAC0 = 0 LCD VAC0 = 1 VAC current Note 1 I VAC0 = 1, V VAC LCD output voltage 1.0 A ...
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... RSL Notes 1. The cycle time (minimum instruction execution time) of the CPU clock ( ) is determined by the oscillation frequency of the connected resonator (and external clock), the system clock control register (SCC) and the processor clock control register (PCC). The figure at the right indicates the cycle time t ...
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SERIAL TRANSFER OPERATION 2-Wire and 3-Wire Serial I/O Mode (SCK...Internal clock output): (T Parameter Symbol SCK cycle time 2.7 to 5.5 V KCY1 DD SCK high-/low-level 2.7 to 5.5 V KL1 KH1 ...
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SBI Mode (SCK...Internal clock output (master)): (T Parameter Symbol SCK cycle time 2.7 to 5.5 V KCY3 DD SCK high-/low-level 2.7 to 5.5 V KL3 KH3 DD width SB0, 1 setup time ...
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AC Timing Test Point (Excluding X1, XT1 Input (MAX Clock Timing X1 Input XT1 Input TI0, TI1, TI2 Timing TI0, TI1, TI2 (MIN.) V (MIN (MAX.) IL (MIN.) V (MIN.) ...
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Serial Transfer Timing 3-wire serial I/O mode SCK SI t KSO1 2-wire serial I/O mode SCK SB0 KCY1 KL1, 2 KH1 SIK1, 2 KSI1, 2 Input Data Output Data ...
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Serial Transfer Timing Bus release signal transfer SCK t t KSB SBL SB0, 1 Command signal transfer SCK t KSB SB0, 1 Interrupt input timing INT0 KR0 to 7 RESET input timing RESET t KCY3 ...
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DATA MEMORY STOP MODE LOW SUPPLY VOLTAGE DATA RETENTION CHARACTERISTICS Parameter Symbol Release signal set time t SREL Oscillation stabilization t Release by RESET WAIT wait time Note 1 Release by interrupt request Notes 1. The oscillation stabilization wait time ...
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Data Retention Timing (STOP Mode Release by RESET STOP Instruction Execution RESET Data Retention Timing (Standby Release Signal: STOP Mode Release by Interrupt Signal STOP Instruction Execution Standby Release Signal (Interrupt Request) Internal Reset Operation STOP ...
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... Note 2 data output hold time MD3 hold time (from MD0 ) MD3 data output float delay time Notes 1. Corresponding symbol of PD27C256A 2. The internal address signal is incremented the rising edge of the fourth X1 input and is not connected to a pin 5˚ 6.0 0. Test conditions MIN ...
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Program Memory Write Timing t VPS VDS D0/P60 to D3/P60 Data input D4/P50 to D7/P53 MD0/P30 t PW MD1/P31 ...
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CHARACTERISTIC CURVES (REFERENCE VALUES 5.0 1.0 0.5 0.1 0.05 0.01 0.005 0.001 (Main System Clock: 6.0-MHz Crystal Resonator Crystal resonator 6.0 MHz ...
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(Main System Clock: 4.19-MHz Crystal Resonator 5.0 1.0 0.5 0.1 0.05 0.01 0.005 0.001 PCC = 0011 PCC = 0010 PCC = 0001 PCC = 0000 Main system clock HALT ...
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PACKAGE DRAWINGS 64 PIN PLASTIC QFP ( 14 NOTE Each lead centerline is located within 0.15 mm (0.006 inch) of its true position (T.P.) at maximum material condition ...
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PIN PLASTIC LQFP ( 12 NOTE Each lead centerline is located within 0.13 mm (0.005 inch) of its true position (T.P.) at maximum material condition ...
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... The PD75P3116 should be soldered and mounted under the conditions recommended in the table below. For details of recommended soldering conditions, refer to the information document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and conditions other than those recommended below, contact an NEC Sales representative. Table 12-1. Surface Mounting Type Soldering Conditions (1) PD75P3116GC-AB8: 64-pin plastic QFP ( mm, 0 ...
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APPENDIX A. FUNCTION LIST OF PD75308B, 753108 AND 75P3116 Parameter Program memory Mask ROM 0000H to 1F7FH (8064 x 8 bits) Data memory CPU 75X Standard Instruction When main system 0.95, 1.91, 15.3 s execution clock is selected (during 4.19-MHz ...
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Parameter Clock output (PCL) • BUZ output (BUZ) 2 kHz (Main system clock: during 4.19-MHz operation) Serial interface 3 modes are available • 3-wire serial I/O mode ··· MSB/LSB can be selected for transfer first bit • 2-wire serial I/O ...
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APPENDIX B. DEVELOPMENT TOOLS The following development tools have been provided for system development using the PD75P3116. In the 75XL series, a common relocatable assembler is used in combination with a device file dedicated to each model. RA75X relocatable assembler ...
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... Hardware PG-1500 This is a PROM writer that can program single-chip microcontroller with PROM in stand-alone mode or under control of host machine when connected with supplied accessory board and optional programmer adapter. It can also program typical PROMs in capacities ranging from 256 bits. ...
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... TGK-064SBW It includes a 64-pin conversion adapter (TGK-064SBW) to facilitate connections with target system. Note 2 Software IE control program This program can control the IE-75000-R or IE-75001 host machine when connected to the IE-75000-R or IE-75001-R via an RS-232C or Centronics interface. Host machine PC-9800 Series IBM PC/AT or compatible Notes 1. ...
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OS for IBM PCs The following operating systems for the IBM PC are supported. OS Version TM PC DOS Ver.3.1 to 6.3, J6.1/V MS-DOS Ver.5.0 to 6.2 5.0/V Note to 6.2/V Note IBM DOS TM J5.02/V Note Note Only English ...
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... Other Related Documents Document Name IC Package Manual Semiconductor Device Mounting Technology Manual Quality Grades on NEC Semiconductor Devices NEC Semiconductor Device Reliability/Quality Control System Electrostatic Discharge (ESD) Test Guide to Quality Assurance for Semiconductor Devices Microcontroller-related Product Guide Third Party’s Product Caution The above related documents are subject to change without notice ...
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... HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction connection is provided to the input pins possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry ...
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... Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: • Device availability • Ordering information • ...
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... Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance ...