UPD72107GC-3B9 NEC, UPD72107GC-3B9 Datasheet

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UPD72107GC-3B9

Manufacturer Part Number
UPD72107GC-3B9
Description
LAPB controller
Manufacturer
NEC
Datasheet

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Part Number:
UPD72107GC-3B9
Manufacturer:
NEC
Quantity:
20 000
Document No. S12962EJ5V0DS00 (5th edition)
Date Published October 1998 N CP(K)
Printed in Japan
chip.
FEATURES
• Complied with ITU-T recommended X.25 (LAP-B84
• ITU-T recommended X.75 supported
• TTC standard JT-T90 supported
• Optional functions
• Powerful test functions
• Abundant statistical information
• Detailed mode setting function
• Modem control function
• On-chip DMAC (Direct Memory Access Controller)
ORDERING INFORMATION
edition)
HDLC frame control
Sequence control
Flow control
Option frame
Global address frame
Error check deletion frame
Data loopback function
Loopback test link function
Frame trace function
24-bit address
Byte/word transfer enabled (switch with external pin)
The PD72107 is an LSI that supports LAP-B protocol specified by the ITU-T recommended X.25 on a single
PD72107CW
PD72107GC-3B9
PD72107L
Part Number
Link Access Procedure Balanced mode
The information in this document is subject to change without notice.
64-pin plastic shrink DIP (750 mils)
80-pin plastic QFP (14 x 14 mm)
68-pin plastic QFJ (950 x 950 mils)
LAP-B CONTROLLER
DATA SHEET
Package
• Memory-based interface
• MAX.4 Mbps serial transfer rate
• NRZ, NRZI coding
Memory-based command
Memory-based status
Memory-based transmit/receive data
MOS INTEGRATED CIRCUIT
PD72107
©
1998

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UPD72107GC-3B9 Summary of contents

Page 1

Link Access Procedure Balanced mode The PD72107 is an LSI that supports LAP-B protocol specified by the ITU-T recommended X. single chip. FEATURES • Complied with ITU-T recommended X.25 (LAP-B84 edition) HDLC frame control Sequence control Flow control ...

Page 2

... Converts the contents of TxFIFO into an HDLC frame and transmits it as serial data Receiver Receives HDLC frame and writes internal data to RxFIFO Internal bus An 8-bit address bus and 8-bit data bus that connect the internal controller, DMAC, FIFO, serial block, and bus interface block 2 Internal controller ...

Page 3

PIN CONFIGURATION (Top View) 64-pin plastic shrink DIP (750 mils) PD72107CW IC 1 RxC 2 RxD 3 TxC 4 TxD 5 CTS RESET B CLK 13 GND 14 A0 ...

Page 4

QFP (14 14 mm) PD72107GC-3B9 HLDRQ 2 HLDAK 3 READY 4 ASTB 5 AEN 6 NC ...

Page 5

QFJ (950 950 mils) PD72107L RESET B CLK 14 GND 15 GND ...

Page 6

PINS 1.1 Pin Functions SDIP QFP Pin Name Pin No. Pin No. Pin No GND CLK 13 26 (Clock) RESET 8 22 (Reset (Pull Up) CS ...

Page 7

... I/O Level 1 – – Use this pin open – – Do not connect anything to this pin I/O L/H When bus master (output) 3-state The signal output from this pin changes according to the input value of the B/W pin. • Byte transfer mode (B UBE is always high impedance. ...

Page 8

SDIP QFP Pin Name Pin No. Pin No. Pin No. B (Byte/Word) READY 59 4 (Ready) HLDRQ 57 2 (Hold Request) HLDAK 58 3 (Hold Acknowledge) AEN 61 6 (Address Enable) A0, A1 15 ...

Page 9

SDIP QFP Pin Name Pin No. Pin No. Pin No. A16D8 to A23D15 (except 50, (except 35) 3-state 51, 55 ...

Page 10

SDIP QFP Pin Name Pin No. Pin No. Pin No. RTS 64 10 (Request To Send (Carrier Detect) TxD 5 17 (Transmit Data) TxC 4 16 (Transmit Clock) Remark LCW: abbreviation for Link Command Word 10 QFJ ...

Page 11

SDIP QFP Pin Name Pin No. Pin No. Pin No. RxD 3 14 (Receive Data) RxC 2 13 (Receive Clock) Remark LCW: abbreviation for Link Command Word 1.2 Pin Status after Reset of PD72107 The status of the output pins ...

Page 12

ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings ( Parameter Symbol Power supply voltage V DD Input voltage V I Output voltage V O Operating ambient temperature T A Storage temperature T stg Caution Product quality may suffer ...

Page 13

AC Characteristics (T = – When bus master (1) Parameter Symbol CLK cycle time t CYK CLK low-level time t KKL CLK high-level time t KKH CLK rise time t KR CLK fall time t ...

Page 14

When bus master (2) Parameter Symbol HLDRQ delay time (vs. CLK ) t DHQH HLDRQ delay time (vs. CLK ) t DHQL HLDAK setup time (vs. CLK ) t SHA HLDAK hold time (vs. CLK ) t HHA AEN delay ...

Page 15

CLK t DHQH HLDRQ t SHA t HHA HLDAK t DAEH AEN ASTB Hi-Z A16D8-A23D15 Hi-Z A0, A1/A2-A15 UBE Hi-Z MWR READY Hi-Z A16D8-A23D15 Hi-Z MRD t DSTL t DSTH t STSTH t DA Address Output data t t SAST ...

Page 16

When bus slave (1) Parameter Symbol IOWR low-level width t WWL CS low-level hold time t HWCS (vs. IOWR ) ADR/UBE/CS low-level setup time t SAW (vs. IOWR ) ADR/UBE hold time (vs. IOWR ) t HWA Data setup time ...

Page 17

When bus slave CS t SAW IOWR A0-A23 UBE D0-D15 CS A0-A23 IORD Hi-Z D0-D15 V DD RESET IORD/IOWR IORD t RVWR IOWR t t WWL HWCS t HWA t t SDW HWD t SAR t RRL t t DRD ...

Page 18

When bus slave (2) Parameter Symbol IOWR/IORD high-level setup time t SWR (vs. HLDAK ) IOWR/IORD high-level hold time t HWR (vs. AEN ) HLDAK IOWR/IORD AEN IOWR/IORD When bus slave (3) Parameter Symbol CLRINT high-level width t CLCLH INT ...

Page 19

Serial block (1) Parameter Symbol TxC/RxC cycle time t CYS TxC/RxC low-level time t SSL TxC/RxC high-level time t SSH TxC/RxC rise time t SR TxC/RxC fall time t SF TxD delay time (vs. TxC ) t DTXD RxD setup ...

Page 20

Serial block (2) Parameter Symbol RxC cycle time t CYR RxC low-level time t SSRL RxC high-level time t SSRH RxC rise time t SRR RxC fall time t SRF Transmit/receive data cycle t CYD TxC low-level time t TCTCL ...

Page 21

Serial block (3) Parameter Symbol RTS delay time (vs. CLK ) t DRTH RTS delay time (vs. CLK ) t DRTL CD setup time (vs. CLK ) t SCD CD hold time (vs. CLK ) t HCD CTS setup time ...

Page 22

... APPLICATION CIRCUIT EXAMPLE (1) Connection with SIFC ( PD98201) PD72107 TxD RxD LAP-B TxC RxC 22 PD72107 PD98201 BINA BOUT1 SIFC BCLK ...

Page 23

PD72107 System Configuration Example (Local Memory Type) Host processor RD WR MEMR A B MEMW PD71086 IOR OE IOW Decoder AB0-AB7 A B PD71086 AB8-AB15 OE AB16-AB19 A B PD71086 BHE OE DB0-DB15 A B PD71086 OE INT Local Access ...

Page 24

PD72107 System Configuration Example (Main Memory Sharing Type) Host processor PD70116 PD71059 INT INT INTAK INTAK RD WR D0- HLDRQ HLDAK ASTB A16-A19 STB OE AD8-AD15 PD71082 3 AD0-AD7 UBE BUF R/W BUFEN PD71086 INTP ...

Page 25

PACKAGE DRAWINGS 64 PIN PLASTIC SHRINK DIP (750 mil NOTES 1. Controlling dimension millimeter. 2. Each lead centerline is located within 0.17 mm (0.007 inch) of its true position ...

Page 26

PIN PLASTIC QFP (14x14 NOTE Each lead centerline is located within 0.13 mm (0.005 inch) of its true position (T.P.) at maximum material condition ...

Page 27

PIN PLASTIC QFJ (950 x 950 mil NOTES 1. Controlling dimension millimeter. 2. Each lead centerline is located within 0. its true position (T.P.) at maximum material condition. ...

Page 28

... The PD72107 should be soldered and mounted under the following recommended conditions. For the details of the recommended soldering conditions, refer to the document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and conditions other than those recommended below, contact your NEC sales representative. Surface mounting type • ...

Page 29

PD72107 29 ...

Page 30

PD72107 ...

Page 31

... Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction connection is provided to the input pins possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS device behave differently than Bipolar or NMOS devices ...

Page 32

... The export of this product from Japan is prohibited without governmental license. To export or re-export this product from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation ...

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