UPD78P4038GK NEC, UPD78P4038GK Datasheet
UPD78P4038GK
Related parts for UPD78P4038GK
UPD78P4038GK Summary of contents
Page 1
... DD TM • QTOP microcomputer (In the planning phase) Remark The QTOP microcomputer is a microcomputer with a built-in one-time PROM that is totally supported by NEC. The support includes writing application programs, marking, screening, and verification. ORDERING INFORMATION Part number PD78P4038GC-3B9 PD78P4038GC- -3B9 80-pin plastic QFP (14 ...
Page 2
... TQFP (fine pitch) (12 PD78P4038KK-T 80-pin ceramic WQFN (14 Please refer to "Quality Grades on NEC Semiconductor Devices" (Document No. C11531E) published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications. Caution The EPROM versions of the PD78P4038 are not intended for use in mass-produced products; ...
Page 3
SERIES PRODUCT DEVELOPMENT DIAGRAM : Under mass production : Under development Standard models Enhanced internal memory capacity, PD784026 pin compatible with the PD784026 Enhanced A/D, Multimaster I 16-bit timer, and power management 100 pins, enhanced I/O and internal memory ...
Page 4
FUNCTIONS Item Number of basic instructions 113 (mnemonics) General-purpose register 8 bits 16 registers Minimum instruction 125 ns/250 ns/500 ns/1,000 ns (at 32 MHz) execution time Internal PROM 128 Kbytes (Can be changed ...
Page 5
Item Clock output Selected from f Watchdog timer 1 channel Standby HALT/STOP/IDLE mode Interrupt Hardware source 23 (16 internal, 7 external (sampling clock variable input: 1)) Software source BRK instruction, BRKCS instruction, operand error Nonmaskable 1 internal, 1 external Maskable ...
Page 6
DIFFERENCES BETWEEN PD78P4038 AND MASKED ROM PRODUCTS ....................... 2. PIN CONFIGURATION (TOP VIEW) ......................................................................................... 3. BLOCK DIAGRAM ..................................................................................................................... 4. LIST OF PIN FUNCTIONS ......................................................................................................... 4.1 Pins for Normal Operating Mode ................................................................................................... 4.2 Pins for PROM Programming Mode (V 4.2.1 ...
Page 7
DIFFERENCES BETWEEN PD78P4038 AND MASKED ROM PRODUCTS The PD78P4038 is produced by replacing the masked ROM in the PD784035, PD784036, PD784037, or PD784038 with PROM to which data can be written. The functions of the PD78P4038 are the same ...
Page 8
... SS1 P00 12 P01 13 P02 14 P03 15 16 P04 17 P05 18 P06 19 P07 20 P67/REFRQ/HLDAK Note Connect the TEST pin -3B9 12 mm) -BE9 directly ...
Page 9
A8-A19 : Address bus AD0-AD7 : Address/data bus ANI0-ANI7 : Analog input ANO0, ANO1 : Analog output ASCK, ASCK2 : Asynchronous serial clock ASTB : Address strobe AV : Analog power supply DD AV -AV : Reference voltage REF1 REF3 ...
Page 10
... Caution L : Connect these pins separately to the connected to the ground Open : Nothing should be connected on these pins. RESET: Set a low-level input. A0-A16 : Address bus CE : Chip enable D0-D7 : Data bus OE : Output enable ...
Page 11
BLOCK DIAGRAM NMI Programmable interrupt controller INTP0-INTP5 INTP3 Timer/counter 0 TO0 (16 bits) TO1 Timer/counter 1 INTP0 (16 bits) INTP1 INTP2/CI Timer/counter 2 TO2 (16 bits) TO3 Timer 3 (16 bits) P00-P03 Real-time output port P04-P07 PWM0 PWM PWM1 ...
Page 12
LIST OF PIN FUNCTIONS 4.1 Pins for Normal Operating Mode (1) Port pins (1/2) Pin I/O Alternate-Function P00-P07 I/O – P10 I/O PWM0 P11 PWM1 P12 ASCK2/SCK2 P13 R D2/SI2 X P14 T D2/SO2 X P15-P17 – P20 Input ...
Page 13
Port pins (2/2) Pin I/O Alternate-Function P50-P57 I/O A8-A15 P60-P63 I/O A16-A19 RD P64 P65 WR P66 WAIT/HLDRQ P67 REFRQ/HLDAK P70-P77 I/O ANI0-ANI7 Function Port 5 (P5): 8-bit I/O port. Inputs and outputs can be specified bit by bit. ...
Page 14
... Strobe signal output for reading the contents of external memory Strobe signal output for writing on external memory Wait signal insertion Refresh pulse output to external pseudo static memory Input of bus hold request Output of bus hold response Latch timing output of time multiplexing address (A0-A7) (for connecting external memory) Clock output PD78P4038 – – ...
Page 15
... Ground for the A/D converter Positive power supply of the port part Positive power supply except for the port part Ground of the port part Ground except for the port part Directly connect (The TEST pin is for the IC test.) SS0 pin. DD1 pin. ...
Page 16
Pin functions (1) V (Programming power supply): Input PP Input pin for setting the PD78P4038 to the PROM programming mode. When the input voltage on this pin more and when RESET input goes low, the ...
Page 17
... P40/AD0-P47/AD7 P50/A8-P57/A15 P60/A16-P63/A19 P64/RD P65/WR P66/WAIT/HLDRQ P67/REFRQ/HLDAK P70/ANI0-P77/ANI7 20-A ANO0, ANO1 12 ASTB/CLKOUT 4-B I/O Recommended Connection Method for Unused Pins I/O Input state connected to V Output state left open Input To be connected DD0 SS0 To be connected to V DD0 I/O Input state: ...
Page 18
... Caution When the I/O mode of an I/O alternate-function pin is unpredictable, connect the pin to V through a resistor 100 kilohms (particularly when the voltage of the reset input pin becomes higher than that of the low level input at power-on or when I/O is switched by software). Remark Since type numbers are consistent in the 78K Series, those numbers are not always serial in each product ...
Page 19
Figure 4-1. I/O Circuits for Pins Type 1-A V DD0 SS0 Type 2 IN Schmitt trigger input with hysteresis characteristics Type 4-B V DD0 Data P Output N disable V SS0 Push-pull output which can output ...
Page 20
INTERNAL MEMORY SWITCHING REGISTER (IMS) This register enables the software to avoid using part of the internal memory. IMS can be set to establish the same memory mapping as used in ROM products that have different internal memory (ROM ...
Page 21
PROM PROGRAMMING The PD78P4038 has an on-chip 128-KB PROM device for use as program memory. When programming, set the V and RESET pins for PROM programming mode. See (2) in Chapter 2 with regard to handling of other, unused ...
Page 22
... Set PGM to H, and set program verify mode. Use verify mode for verification following each write operation. (8) Program inhibit mode Program inhibit mode is used to write to a single device when several PD78P4038 devices are connected in parallel and pins. ...
Page 23
PROM Write Sequence Figure 6-1. Page Program Mode Flowchart V DD Address = Address + Pass Remark G = Start address N = Program end address Start Address = +12.5 ...
Page 24
Figure 6-2. Page Program Mode Timing Page data latch A2-A16 A0, A1 D0-D7 Data input +1 PGM ...
Page 25
Figure 6-3. Byte Program Mode Flowchart 0.1-ms program pulse Address = Address + Pass Remark G = Start address N = Program end address Start Address = G = +12.5 ...
Page 26
Figure 6-4. Byte Program Mode Timing Program A0-A16 D0-D7 Data input +1 PGM Cautions ...
Page 27
PROM Read Sequence Follow this sequence to read the PROM contents to an external data bus (D0 to D7). (1) Set the RESET pin to low level and add + the V other, unused pins. (2) Add ...
Page 28
... SCREENING ONE-TIME PROM PRODUCTS NEC cannot execute a complete test of one-time PROM products ( PD78P4038GC-3B9, PD78P4038GC-8BT, and PD78P4038GK-BE9) due to their structure before shipment recommended that you screen (verify) PROM products after writing necessary data into them and storing them at 125 C for 24 hours min ...
Page 29
ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS (T Parameter Symbol Supply voltage Input voltage Output voltage V O Output low current I OL Output high current I OH A/D converter reference ...
Page 30
OPERATING CONDITIONS • Operating ambient temperature (T • Rise time and fall time ( (at pins which are not specified 200 • Power supply voltage and clock cycle time Figure 11-1. ...
Page 31
... Never cause the wires to run near a line carrying a large varying current. • Cause the grounding point of the capacitor of the oscillator circuit to have the same potential Never connect the capacitor to a ground pattern carrying a large current. SS1 • Never extract a signal from the oscillator. ...
Page 32
... Never cause the wires to run near a line carrying a large varying current. • Cause the grounding point of the capacitor of the oscillator circuit to have the same potential Never connect the capacitor to a ground pattern carrying a large current. SS1 • Never extract a signal from the oscillator. ...
Page 33
DC CHARACTERISTICS (T = – Parameter Symbol Input low voltage V For pins other than those described in IL1 Notes and 4 V For pins described in Notes and ...
Page 34
DC CHARACTERISTICS (T = – Parameter Symbol Input leakage current L| For pins other than X1 when EXTC = 0 Output leakage current Operation mode V supply ...
Page 35
AC CHARACTERISTICS (T = – (1) Read/write operation (1/2) Parameter Symbol Address setup time t V SAST ASTB high-level width t V WSTH Address hold time (to ASTB ) t V HSTLA Address hold time ...
Page 36
Read/write operation (2/2) Parameter Symbol Data setup time ( SODW Note Data hold time ( HWOD Delay from WR to ASTB t DWST WR low-level width t V WWL Note The ...
Page 37
External wait timing Symbol Parameter t Delay from address to WAIT input V DAWT Delay from ASTB to WAIT input t V DSTWT t Hold time from ASTB to WAIT V HSTWTH Delay from ASTB to WAIT t V ...
Page 38
SERIAL OPERATION (T = – (1) CSI Parameter Symbol Serial clock cycle time (SCK0) t CYSK0 Serial clock low-level width t WSKL0 (SCK0) Serial clock high-level width t WSKH0 (SCK0) SI0 setup time (to SCK0 ...
Page 39
IOE1, IOE2 Parameter Symbol Serial clock cycle time t Input CYSK1 (SCK1, SCK2) Output Serial clock low-level width t Input WSKL1 (SCK1, SCK2) Output Serial clock high-level width t Input WSKH1 (SCK1, SCK2) Output Setup time for SI1 and ...
Page 40
CLOCK OUTPUT OPERATION Parameter Symbol CLKOUT cycle time t CYCL t CLKOUT low-level width V CLL CLKOUT high-level width t V CLH t CLKOUT rise time V CLR CLKOUT fall time t V CLF Remarks n: Divided frequency ratio set ...
Page 41
A/D CONVERTER CHARACTERISTICS (T = – Symbol Parameter Resolution V Total error Note – Linearity calibration Note Quantization error Conversion ...
Page 42
D/A CONVERTER CHARACTERISTICS (T Parameter Symbol Resolution Total error Load conditions Load conditions Settling time Load conditions Output resistance R DACS0 ...
Page 43
DATA RETENTION CHARACTERISTICS (T Parameter Symbol Data retention voltage V STOP mode DDDR Data retention current I V DDDR DDDR V DDDR V rise time t RVD DD V fall time t DD FVD V hold time t DD HVD ...
Page 44
TIMING WAVEFORM (1) Read operation t WSTH ASTB t SAST t HSTLA A8-A19 AD0-AD7 t DSTR t DAR RD (2) Write operation t WSTH ASTB t SAST t HSTLA A8-A19 AD0-AD7 t DSTW t DAW DSTID t ...
Page 45
HOLD TIMING ADTB, A8-A19, AD0-AD7, RD FHQC t DCFHA HLDRQ t DHQHHAH HLDAK EXTERNAL WAIT SIGNAL INPUT TIMING (1) Read operation ASTB t DSTWT A8-A19 AD0-AD7 t DAWT RD WAIT (2) Write operation ASTB t DSTWT A8-A19 AD0-AD7 ...
Page 46
REFRESH TIMING WAVEFORM (1) Random read/write cycle t RC ASTB (2) When refresh memory is accessed for a read and write at the same time ASTB RD DSTRFQ REFRQ t WRFQL (3) Refresh after ...
Page 47
SERIAL OPERATION (1) CSI t WSKL0 SCK t CYSK0 SI SO (2) IOE1, IOE2 t WSKL1 SCK t CYSK1 SI SO (3) UART, UART2 ASCK, ASCK2 t WSKH0 t DSBSK1 Output data t WSKH1 t t HSOSK DSOSK Output data ...
Page 48
CLOCK OUTPUT TIMING CLKOUT t CLR INTERRUPT INPUT TIMING NMI INTP0 CI, INTP1-INTP3 INTP4, INTP5 RESET INPUT TIMING RESET CLH CLL t CLF t CYCL t t WNIH WNIL t t WIT0H WIT0L t t WIT1H WIT1L ...
Page 49
EXTERNAL CLOCK TIMING DATA RETENTION CHARACTERISTICS STOP mode setting HVD FVD RESET NMI (Clearing by falling edge) NMI (Clearing by rising edge WXH WXH CYX V DDDR t ...
Page 50
DC PROGRAMMING CHARACTERISTICS (T Parameter Symbol Symbol High-level input voltage Low-level input voltage Input leakage current I I LIP LI V High-level output voltage Low-level output ...
Page 51
AC PROGRAMMING CHARACTERISTICS (T PROM Write Mode (Page Program Mode) Parameter Symbol Address setup time CE set time Input data setup time Address hold time Input data hold time Output data hold time V setup time PP V setup time ...
Page 52
PROM Write Mode (Byte Program Mode) Parameter Symbol Address setup time CE set time Input data setup time Address hold time Input data hold time Output data hold time V setup time PP V setup time DDP Initial program pulse ...
Page 53
PROM Write Mode Timing (Page Program Mode) Page data latch A2-A16 AHL A0 Hi-Z D0-D7 t Data input VPS DDP t VDS V + 1.5 DDP V ...
Page 54
PROM Write Mode Timing (Byte Program Mode) A0-A16 t AS Hi-Z D0- DDP t VPS V + 1.5 DDP V DDP V DDP t VDS ...
Page 55
PACKAGE DRAWINGS 80 PIN PLASTIC QFP (14x14 NOTE Each lead centerline is located within 0.13 mm (0.005 inch) of its true position (T.P.) at maximum material condition ...
Page 56
PIN PLASTIC QFP (14 14 NOTE Each lead centerline is located within 0.13 mm (0.005 inch) of its true position (T.P.) at maximum material condition ...
Page 57
PIN PLASTIC TQFP (FINE PITCH) (12 12 NOTE Each lead centerline is located within 0.10 mm (0.004 inch) of its true position (T.P.) at maximum material condition ...
Page 58
PIN CERAMIC WQFN NOTE Each lead centerline is located within 0.06 mm (0.003 inch) of its true position (T.P.) at maximum material condition ITEM MILLIMETERS 14.0 0.2 0.551 ...
Page 59
RECOMMENDED SOLDERING CONDITIONS The conditions listed below shall be met when soldering the PD78P4038. For details of the recommended soldering conditions, refer to our document Semiconductor Device Mounting Technology Manual (C10535E). Please consult with our sales offices in case ...
Page 60
Table 13-1. Soldering Conditions for Surface-Mount Devices (2/2) (3) PD78P4038GK-BE9: 80-pin plastic TQFP (fine pitch) (12 Soldering Process Infrared ray reflow Peak package's surface temperature: 235 C Reflow time: 30 seconds or less (210 C or more) Maximum allowable number ...
Page 61
... C compiler package for all 78K/IV Series models Device file for PD784038 Subseries models C compiler library source file for all 78K/IV Series models PROM programmer Programmer adaptor, connects to PG-1500 Control program for PG-1500 In-circuit emulator for all 78K/IV Series models Power supply unit for IE-78K4-NS ...
Page 62
When using the in-circuit emulator IE-784000-R IE-784000-R IE-70000-98-IF-B IE-70000-98-IF-C IE-70000-98N-IF IE-70000-PC-IF-B IE-70000-PC-IF-C IE-78000-R-SV3 Note IE-784038-NS-EM1 IE-784038-R-EM1 IE-78400-R-EM Note IE-78K4-R-EX2 EP-78230GC-R EP-78054GK-R EV-9200GC-80 TGK-080SDW EV-9900 ID78K4 SM78K4 DF784038 Note Under development (4) Real-time OS RX78K/IV MX78K4 62 In-circuit emulator for ...
Page 63
... The ID78K4-NS, ID78K4, and SM78K4 can be used in combination with the DF784038. • The CC78K4 and RX78K/IV can be used in combination with the RA78K4 and DF784038. • The NP-80GC is a product from Naito Densei Machida Mfg. Co., Ltd. (044-822-3813). Consult the NEC sales representative for purchasing. ...
Page 64
... APPENDIX B CONVERSION SOCKET (EV-9200GC-80) AND CONVERSION ADAPTER (TGK-080SDW) (1) Conversion socket (EV-9200GC-80) package drawings and recommended pattern to mount the socket Connect the PD78P4038YKK-T (80-pin ceramic WQFN (14 in combination with the EV-9200GC-80. Figure B-1. Package Drawings of EV-9200GC-80 (Reference) (unit: mm) Based on EV-9200GC-80 (1) Package drawing (in mm) ...
Page 65
Figure B-2. Recommended Pattern to Mount EV-9200GC- Substrate (Reference) (unit: mm) Based on EV-9200GC-80 (2) Pad drawing (in mm) ITEM MILLIMETERS A 19.7 B 15.0 C 0.65 0.02 19=12.35 0.05 D 0.65 0.02 19=12.35 0.05 E 15.0 F ...
Page 66
... Conversion adapter (TGK-080SDW) package drawings Connect the PD78P4038GK-BE9 (80-pin plastic TQFP (fine pitch: 12 combination with the TGK-080SDW. Figure B-3. Package Drawings of TGK-080SDW (Reference) (unit: mm) TGK-080SDW (TQPACK080SD + TQSOCKET080SDW) Package dimension (unit: mm screw Protrusion : 4 places ...
Page 67
APPENDIX C RELATED DOCUMENTS Documents Related to Devices Document Name PD784031 Data Sheet PD784035, 784036, 784037, 784038 Data Sheet PD78P4038 Data Sheet PD784038, 784038Y Sub-Series User's Manual, Hardware PD784038 Sub-Series Special Function Registers 78K/IV Series User's Manual, Instruction 78K/IV Series ...
Page 68
... Document Name IC PACKAGE MANUAL Semiconductor Device Mounting Technology Manual Quality Grades on NEC Semiconductor Device NEC Semiconductor Device Reliability/Quality Control System Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) Semiconductor Device Quality Control/Reliability Handbook Guide for Products Related to Microcomputer: Other Companies Caution The above documents may be revised without notice ...
Page 69
... Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction connection is provided to the input pins possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS device behave differently than Bipolar or NMOS devices ...
Page 70
... IEBus and QTOP are trademarks of NEC Corporation. MS-DOS and Windows are either registered trademarks or trademarks of Microsoft Corporation in the United States and/or other countries. PC/AT and PC DOS are trademarks of IBM Corporation. HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company. SPARCstation is a trademark of SPARC International, Inc. ...
Page 71
... Regional Information Some information contained in this document may vary from country to country. Before using any NEC product in your application, pIease contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify: Device availability • Ordering information • ...
Page 72
... The export of these products from Japan is regulated by the Japanese government. The export of some or all of these products may be prohibited without governmental license. To export or re-export some or all of these products from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative. ...