UPD78F0537DGA(T)-9EV-A NEC, UPD78F0537DGA(T)-9EV-A Datasheet
UPD78F0537DGA(T)-9EV-A
Specifications of UPD78F0537DGA(T)-9EV-A
Related parts for UPD78F0537DGA(T)-9EV-A
UPD78F0537DGA(T)-9EV-A Summary of contents
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... Do not use this product for mass production because its reliability cannot be guaranteed after the on-chip debug function has been used, due to issues with respect to the number of times the flash memory can be rewritten. NEC Electronics does not accept complaints concerning this product. ...
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User’s Manual U17260EJ6V0UD ...
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... IH 2 HANDLING OF UNUSED INPUT PINS Unconnected CMOS device inputs can be cause of malfunction input pin is unconnected possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using pull-up or pull-down circuitry ...
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... EEPROM is a trademark of NEC Electronics Corporation. Windows and Windows NT are registered trademarks or trademarks of Microsoft Corporation in the United States and/or other countries. PC/ trademark of International Business Machines Corporation. HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company. SPARCstation is a trademark of SPARC International, Inc. ...
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... NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others. • ...
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Readers This manual is intended for user engineers who wish to understand the functions of the 78K0/KE2 and design and develop application systems and programs for these devices. The target products are as follows. 78K0/KE2: <R> Purpose This manual is ...
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... Flash Memory Self Programming User’s Manual <R> TM 78K0/Kx2 EEPROM Emulation Application Note Note This document is under engineering management. For details, consult an NEC Documents Related to Development Tools (Software) (User’s Manuals) RA78K0 Ver. 3.80 Assembler Package CC78K0 Ver. 3.70 C Compiler SM+ System Simulator ID78K0-QB Ver ...
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... NEC Semiconductor Device Reliability/Quality Control System Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) Note See the “Semiconductor Device Mount Manual” website (http://www.necel.com/pkg/en/mount/index.html). Caution The related documents listed above are subject to change without notice. Be sure to use the latest version of each document when designing ...
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... DD DD 2.2.17 V and EV ................................................................................................................................. 2.2.18 FLMD0 ...........................................................................................................................................42 2.3 Pin I/O Circuits and Recommended Connection of Unused Pins........................................... 43 CHAPTER 3 CPU ARCHITECTURE...................................................................................................... 47 3.1 Memory Space .............................................................................................................................. 47 3.1.1 Internal program memory space ......................................................................................................58 µ 3.1.2 Memory bank ( PD78F0536, 78F0537, and 78F0537D only) .........................................................60 3.1.3 Internal data memory space ............................................................................................................60 3.1.4 Special function register (SFR) area ................................................................................................61 3 ...
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Immediate addressing..................................................................................................................... 80 3.3.3 Table indirect addressing ................................................................................................................ 81 3.3.4 Register addressing ........................................................................................................................ 82 3.4 Operand Address Addressing .................................................................................................... 82 3.4.1 Implied addressing .......................................................................................................................... 82 3.4.2 Register addressing ........................................................................................................................ 83 3.4.3 Direct addressing ............................................................................................................................ 84 3.4.4 Short direct addressing ...
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Configuration of Clock Generator ............................................................................................ 141 6.3 Registers Controlling Clock Generator ................................................................................... 143 6.4 System Clock Oscillator ............................................................................................................ 152 6.4.1 X1 oscillator ...................................................................................................................................152 6.4.2 XT1 oscillator .................................................................................................................................152 6.4.3 When subsystem clock is not used ................................................................................................155 6.4.4 Internal high-speed oscillator ...
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Cautions for 8-Bit Timer/Event Counters 50 and 51 ............................................................... 267 CHAPTER 9 8-BIT TIMERS H0 AND H1 .......................................................................................... 268 9.1 Functions of 8-Bit Timers H0 and H1 ....................................................................................... 268 9.2 Configuration of 8-Bit Timers H0 and H1 ................................................................................. 268 ...
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CHAPTER 14 SERIAL INTERFACE UART0 ...................................................................................... 334 14.1 Functions of Serial Interface UART0...................................................................................... 334 14.2 Configuration of Serial Interface UART0 ............................................................................... 335 14.3 Registers Controlling Serial Interface UART0....................................................................... 338 14.4 Operation of Serial Interface UART0...................................................................................... 343 14.4.1 Operation stop mode ...
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Communication reservation........................................................................................................446 17.5.15 Other cautions............................................................................................................................449 17.5.16 Communication operations.........................................................................................................451 2 17.5.17 Timing interrupt request (INTIIC0) occurrence .................................................................459 17.6 Timing Charts ........................................................................................................................... 480 CHAPTER 18 MULTIPLIER/DIVIDER ( 78F0537D ONLY) .......................................................................................................... 487 18.1 Functions of Multiplier/Divider................................................................................................ 487 18.2 Configuration ...
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... Processing Time for Each Command When PG-FP4 Is Used (Reference) ........................ 586 26.10 Flash Memory Programming by Self-Programming ........................................................... 588 26.10.1 Boot swap function.....................................................................................................................595 CHAPTER 27 ON-CHIP DEBUG FUNCTION ( 27.1 Connecting QB-78K0MINI or QB-MINI2 to 27.2 Reserved Area Used by QB-78K0MINI and QB-MINI2 .......................................................... 599 CHAPTER 28 INSTRUCTION SET ...................................................................................................... 600 28.1 Conventions Used in Operation List...................................................................................... 600 28 ...
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CHAPTER 31 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS: T CHAPTER 32 ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS: T CHAPTER 33 PACKAGE DRAWINGS ................................................................................................ 694 CHAPTER 34 RECOMMENDED SOLDERING CONDITIONS........................................................... 702 CHAPTER 35 CAUTIONS FOR WAIT................................................................................................. 704 35.1 Cautions for Wait...................................................................................................................... 704 35.2 ...
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... PD78F0537D has an on-chip debug function. Do not use this product for mass production because its reliability cannot be guaranteed after the on-chip debug function has been used, from the viewpoint of the restriction on the number of times the flash memory can be rewritten. NEC Electronics does not accept any complaint about this product. ...
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... Watch timer: • Watchdog timer: µ Note PD78F0531, 78F0532, 78F0533: 1 channel Serial interface µ PD78F0531, 78F0532, 78F0533: 3 channels µ PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D: 4 channels • UART (LIN (Local Interconnect Network)-bus supported: 1 channel • CSI/UART Note 1 : • CSI Note 2 : • Notes 1 ...
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... PD78F0537FC-AA1-A Remark Products with -A at the end of the part number are lead-free products " " NEC Corporation to know the specification of quality grade on the devices and its recommended applications. CHAPTER 1 OUTLINE Package 64-pin plastic LQFP(fine pitch) (10x10) 64-pin plastic LQFP (14x14) ...
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... NEC Electronics does not accept complaints about this product. Remark Products with –A and –AX at the end of the part number are lead-free products " " NEC Corporation to know the specification of quality grade on the devices and its recommended applications. 20 CHAPTER 1 OUTLINE Package ...
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... PD78F0537GK(A2)-GAJ-AX Remark Products with –A and –AX at the end of the part number are lead-free products " " NEC Corporation to know the specification of quality grade on the devices and its recommended applications. CHAPTER 1 OUTLINE Package 64-pin plastic LQFP (fine pitch) (10x10) ...
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... PD78F0537D (product with on-chip debug function) only µ 2. PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D only Cautions 1. Make AV and Make EV the same potential Connect the REGC pin ANI0/P20 to ANI7/P27 are set in the analog input mode after release of reset. 22 CHAPTER 1 OUTLINE the same potential ...
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... Notes 1. PD78F0537D (product with on-chip debug function) only µ 2. PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D only Cautions 1. Make AV and Make EV the same potential Connect the REGC pin ANI0/P20 to ANI7/P27 are set in the analog input mode after release of reset. CHAPTER 1 OUTLINE Bottom View ...
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Pin Identification ANI0 to ANI7: Analog input AV : Analog reference voltage REF AV : Analog ground SS BUZ: Buzzer output EV : Power supply for port Ground for port SS EXCLK: External clock input (main system ...
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Microcontroller Lineup ROM RAM 78K0/KB2 30/36 Pins 38/44 Pins − 128 − − − µ µ Note PD78F0503D PD78F0513D ...
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The list of functions in the 78K0/Kx2 microcontrollers is shown below. Part Number Item Flash memory (KB) 8 RAM (KB) 0.5 Bank (flash memory) <R> Power supply voltage Regulator Minimum instruction execution time High-speed system Internal high-speed oscillation Subsystem Internal ...
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Part Number Item Flash memory (KB) RAM (KB) Bank (flash memory) <R> Power supply voltage Regulator Minimum instruction execution time High-speed system Internal high-speed oscillation Subsystem Internal low-speed oscillation Total N-ch O. tolerance) 16 bits (TM0) 8 bits ...
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Block Diagram TO00/TI010/P01 16-bit TIMER/ EVENT COUNTER 00 TI000/P00 (LINSEL) RxD6/P14 (LINSEL) Note2 Note2 TO01 /TI011 /P06 16-bit TIMER/ Note2 TI001 /P05 EVENT COUNTER 01 TOH0/P15 8-bit TIMER H0 TOH1/P16 8-bit TIMER H1 INTERNAL LOW-SPEED OSCILLATOR WATCHDOG TIMER 8-bit ...
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Outline of Functions Item Internal Flash memory memory (self-programming Note 1 supported) Memory bank High-speed RAM Expansion RAM Memory space Main High-speed system system clock Standard clock products, (A) (oscillation grade products frequency) <R> (A2) grade products Internal high-speed ...
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Item Timers Timer outputs Clock output Buzzer output A/D converter Serial interface Multiplier/divider Vectored Internal interrupt sources External Key interrupt Reset On-chip debug function <R> Power supply voltage <R> Operating ambient temperature Package Note Select either of the functions of ...
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An outline of the timer is shown below. 16-Bit Timer/ Event Counters 00 and 01 TM00 Function Interval timer 1 channel External event 1 channel counter PPG output 1 output − PWM output Pulse width 2 inputs measurement Square-wave 1 ...
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Pin Function List There are three types of pin I/O buffer power supplies: AV power supplies and the pins is shown below. Power Supply AV REF (1) Port functions (1/2) Function Name I/O P00 I/O ...
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Port functions (2/2) Function Name I/O P40 to P43 I/O Port 4. 4-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting. P50 to P53 I/O ...
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Non-port functions (1/2) Function Name I/O INTP0 Input External interrupt request input for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be INTP1 specified INTP2 INTP3 INTP4 INTP5 INTP6 INTP7 SI10 Input ...
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... EV Ground potential for ports other than P20 to P27 and P121 to SS P124. Make EV − FLMD0 Flash memory programming mode setting Note OCD0A Input Connection for on-chip debug mode setting pins µ ( PD78F0537D only) Note OCD1A Note − OCD0B Note OCD1B µ ...
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Description of Pin Functions 2.2.1 P00 to P06 (port 0) P00 to P06 function as a 7-bit I/O port. These pins also function as timer I/O, serial interface data I/O, clock I/O, and chip select input. The following operation ...
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P10 to P17 (port 1) P10 to P17 function as an 8-bit I/O port. These pins also function as pins for external interrupt request input, serial interface data I/O, clock I/O, and timer I/O. The following operation modes can ...
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... PD78F0534, 78F0535, 78F0536, and 78F0537) and having a product rank of “I”, “K”, or “E”, and for the product with an on-chip debug function ( connect P31/INTP2/OCD1A memory programmer. • P31/INTP2/OCD1A The above connection is not necessary when writing the flash memory by means of self programming. Note OCD1A is provided to the 38 CHAPTER 2 PIN FUNCTIONS µ ...
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... Remarks 1. For the product ranks, consult an NEC Electronics sales representative. 2. Only for the (OCD1A, OCD1B) when the on-chip debug function is used. For how to connect an in-circuit <R> emulator supporting on-chip debugging (QB-78K0MINI or QB-MINI2), see CHAPTER 27 ON- CHIP DEBUG FUNCTION ( 2.2.5 P40 to P43 (port 4) P40 to P43 function as a 4-bit I/O port ...
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... Note P121/X1/OCD0A programmer. • P121/X1/OCD0A The above connection is not necessary when writing the flash memory by means of self programming. 40 CHAPTER 2 PIN FUNCTIONS as follows when writing the flash memory with a flash memory Note ...
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... Note OCD0A is provided to the Remarks 1. For the product ranks, consult an NEC Electronics sales representative. 2. Only for the (OCD0A, OCD0B) when the on-chip debug function is used. For how to connect an in-circuit <R> emulator supporting on-chip debugging (QB-78K0MINI or QB-MINI2), see CHAPTER 27 ON- CHIP DEBUG FUNCTION ( 2 ...
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... V pin. SS 2.2.14 RESET This is the active-low system reset input pin. 2.2.15 REGC This is the pin for connecting regulator output (2.5 V) stabilization capacitance for internal operation. Connect this µ pin to V via a capacitor (0. recommended). SS Caution Keep the wiring length as short as possible for the broken-line part in the above figure. ...
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... P31/INTP2/OCD1A Note 4 The above connection is not necessary when writing the flash memory by means of self programming. 4. OCD1A and OCD1B are provided to the Remark For the product ranks, consult an NEC CHAPTER 2 PIN FUNCTIONS Table 2-2 ...
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... SS FLMD0 38 RESET 2 Notes 1. Use recommended connection above in I/O port mode (see Figure 6-2 Format of Clock Operation Mode Select Register (OSCCTL)) when these pins are not used. 2. For products without an on-chip debug function and with the flash memory more µ ( PD78F0534, 78F0535, 78F0536, and 78F0537) and having a product rank of “I”, “K”, or “E”, and for the product with an on-chip debug function ( when writing the flash memory with a flash memory programmer ...
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Type 2 IN Schmitt-triggered input with hysteresis characteristics Type 3-C P-ch Data N-ch Type 5-AG Pull-up enable EV DD Data P-ch Output N-ch disable EV SS Input enable CHAPTER 2 PIN FUNCTIONS Figure 2-1. Pin I/O Circuit List (1/2) Type ...
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Type 13-AD Data Output N-ch disable EV SS Input enable Type Data P-ch Output N-ch disable RESET V SS Input enable V DD Data P-ch Output N-ch disable RESET V SS Input enable 46 CHAPTER 2 PIN ...
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Memory Space Products in the 78K0/KE2 can access memory space. Figures 3-1 to 3-8 show the memory maps. Cautions 1. Regardless of the internal memory capacity, the initial values of the internal memory size switching register ...
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Special function registers (SFR) 256 x 8 bits General-purpose registers bits Internal ...
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Special function registers (SFR) 256 x 8 bits General-purpose registers bits Internal ...
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Special function registers (SFR) 256 x 8 bits General-purpose registers bits Internal ...
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Special function registers (SFR) 256 x 8 bits General-purpose registers bits Internal ...
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Special function registers (SFR) 256 x 8 bits General-purpose registers bits Internal ...
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Special function registers (SFR) 256 x 8 bits General-purpose registers bits Internal ...
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Special function registers (SFR) 256 x 8 bits General-purpose registers bits Internal ...
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Figure 3-8. Memory Map ( PD78F0537D Special function registers (SFR) 256 x 8 bits General-purpose registers bits ...
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Correspondence between the address values and block numbers in the flash memory are shown below. Table 3-2. Correspondence Between Address Values and Block Numbers in Flash Memory (1/2) (1) PD78F0531, 78F0532, 78F0533, 78F0534, 78F0535 Address Value Block Address Value Number ...
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Table 3-2. Correspondence Between Address Values and Block Numbers in Flash Memory (2/2) (2) PD78F0536, 78F0537, 78F0537D Address Value Block Address Value Number 0000H to 03FFH 00H 8000H to 83FFH 0400H to 07FFH 01H 8400H to 87FFH 0800H to 0BFFH ...
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Internal program memory space The internal program memory space stores the program and table data. Normally addressed with the program counter (PC). 78K0/KE2 products incorporate internal ROM (flash memory), as shown below. Part Number Structure PD78F0531 Flash ...
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Vector Table Address Interrupt Source 0000H RESET input, POC, LVI, WDT 0004H INTLVI 0006H INTP0 0008H INTP1 000AH INTP2 000CH INTP3 000EH INTP4 0010H INTP5 0012H INTSRE6 0014H INTSR6 0016H INTST6 0018H INTCSI10/INTST0 001AH INTTMH1 001CH INTTMH0 001EH INTTM50 Note ...
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Memory bank ( PD78F0536, 78F0537, and 78F0537D only) The 16 KB area 8000H to BFFFH is assigned to memory banks the PD78F0536, and assigned to memory banks the PD78F0537 and 78F0537D. ...
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Internal expansion RAM Table 3-6. Internal Expansion RAM Capacity Part Number µ PD78F0531 µ PD78F0532 µ PD78F0533 µ PD78F0534 µ PD78F0535 µ PD78F0536 µ PD78F0537, 78F0537D The internal expansion RAM can also be used as a normal data area ...
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Figure 3-9. Correspondence Between Data Memory and Addressing ( PD78F0531 Special function registers (SFR) 256 x 8 bits ...
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CHAPTER 3 CPU ARCHITECTURE Figure 3-10. Correspondence Between Data Memory and Addressing ( PD78F0532 Special function registers (SFR) 256 x 8 bits ...
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Figure 3-11. Correspondence Between Data Memory and Addressing ( PD78F0533 Special function registers (SFR) 256 x 8 bits ...
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CHAPTER 3 CPU ARCHITECTURE Figure 3-12. Correspondence Between Data Memory and Addressing ( PD78F0534 Special function registers (SFR) 256 x 8 bits ...
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Figure 3-13. Correspondence Between Data Memory and Addressing ( PD78F0535 Special function registers (SFR) 256 x 8 bits ...
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Figure 3-14. Correspondence Between Data Memory and Addressing ( PD78F0536 Special function registers (SFR) 256 x 8 bits ...
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Figure 3-15. Correspondence Between Data Memory and Addressing ( PD78F0537, 78F0537D Special function registers (SFR) 256 x 8 bits ...
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Processor Registers The 78K0/KE2 products incorporate the following processor registers. 3.2.1 Control registers The control registers control the program sequence, statuses and stack memory. The control registers consist of a program counter (PC), a program status word (PSW) and ...
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Zero flag (Z) When the operation result is zero, this flag is set (1 reset (0) in all other cases. (c) Register bank select flags (RBS0 and RBS1) These are 2-bit flags to select one of the ...
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CHAPTER 3 CPU ARCHITECTURE Figure 3-19. Data to Be Saved to Stack Memory (a) PUSH rp instruction (when SP = FEE0H) FEE0H FEE0H SP FEDFH FEDEH SP FEDEH (b) CALL, CALLF, CALLT instructions (when SP = FEE0H) SP FEE0H FEE0H ...
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Figure 3-20. Data to Be Restored from Stack Memory (a) POP rp instruction (when SP = FEDEH (c) RETI, RETB instructions (when SP = FEDDH CHAPTER 3 CPU ARCHITECTURE FEE0H FEE0H FEDFH Register ...
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General-purpose registers General-purpose registers are mapped at particular addresses (FEE0H to FEFFH) of the data memory. The general-purpose registers consists of 4 banks, each bank consisting of eight 8-bit registers ( and H). ...
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Special function registers (SFRs) Unlike a general-purpose register, each special function register has a special function. SFRs are allocated to the FF00H to FFFFH area. Special function registers can be manipulated like general-purpose registers, using operation, transfer, and bit ...
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Table 3-7. Special Function Register List (1/4) Address Special Function Register (SFR) Name FF00H Port register 0 FF01H Port register 1 FF02H Port register 2 FF03H Port register 3 FF04H Port register 4 FF05H Port register 5 FF06H Port register ...
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Table 3-7. Special Function Register List (2/4) Address Special Function Register (SFR) Name FF30H Pull-up resistor option register 0 FF31H Pull-up resistor option register 1 FF33H Pull-up resistor option register 3 FF34H Pull-up resistor option register 4 FF35H Pull-up resistor ...
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Table 3-7. Special Function Register List (3/4) Address Special Function Register (SFR) Name FF70H Asynchronous serial interface operation mode register 0 FF71H Baud rate generator control register 0 FF72H Receive buffer register 0 FF73H Asynchronous serial interface reception error status ...
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Table 3-6. Special Function Register List (4/4) Address Special Function Register (SFR) Name FFBBH Prescaler mode register 00 FFBCH Capture/compare control register 00 FFBDH 16-bit timer output control register 00 FFBEH Low-voltage detection register FFBFH Low-voltage detection level selection register ...
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Instruction Address Addressing An instruction address is determined by contents of the program counter (PC) and memory bank select register (BANK), and is normally incremented (+1 for each byte) automatically according to the number of bytes of an instruction ...
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Immediate addressing [Function] Immediate data in the instruction word is transferred to the program counter (PC) and branched. This function is carried out when the CALL !addr16 or BR !addr16 or CALLF !addr11 instruction is executed. CALL !addr16 and ...
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Table indirect addressing [Function] Table contents (branch destination address) of the particular location to be addressed by bits the immediate data of an operation code are transferred to the program counter (PC) and branched. This ...
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... ROR4/ROL4 A register for storage of digit data that undergoes digit rotation [Operand format] Because implied addressing can be automatically determined with an instruction, no particular operand format is necessary. [Description example] In the case of MULU X With an 8-bit 8-bit multiply instruction, the product of A register and X register is stored in AX. In this example, the A and AX registers are specified by implied addressing ...
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Register addressing [Function] The general-purpose register to be specified is accessed as an operand with the register bank select flags (RBS0 to RBS1) and the register specify codes of an operation code. Register addressing is carried out when an ...
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Direct addressing [Function] The memory to be manipulated is directly addressed with immediate data in an instruction word becoming an operand address. This addressing can be carried out for all of the memory spaces. However, before addressing a memory ...
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Short direct addressing [Function] The memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word. This addressing is applied to the 256-byte space FE20H to FF1FH. Internal high-speed RAM and special ...
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Special function register (SFR) addressing [Function] A memory-mapped special function register (SFR) is addressed with 8-bit immediate data in an instruction word. This addressing is applied to the 240-byte spaces FF00H to FFCFH and FFE0H to FFFFH. However, the ...
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Register indirect addressing [Function] Register pair contents specified by a register pair specify code in an instruction word and by a register bank select flag (RBS0 and RBS1) serve as an operand address for addressing the memory. This addressing ...
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Based addressing [Function] 8-bit immediate data is added as offset data to the contents of the base register, that is, the HL register pair in the register bank specified by the register bank select flag (RBS0 and RBS1), and ...
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Based indexed addressing [Function] The register contents specified in an instruction word are added to the contents of the base register, that is, the HL register pair in the register bank specified by the register bank ...
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Stack addressing [Function] The stack area is indirectly addressed with the stack pointer (SP) contents. This addressing method is automatically employed when the PUSH, POP, subroutine call and return instructions are executed or the register is saved/reset upon generation ...
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CHAPTER 4 MEMORY BANK SELECT FUNCTION µ ( PD78F0536, 78F0537, AND 78F0537D ONLY) 4.1 Memory Bank µ The PD78F0536, 78F0537, and 78F0537D implement a ROM capacity 128 KB by selecting a memory bank from a memory ...
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CHAPTER 4 MEMORY BANK SELECT FUNCTION ( 4.2 Difference in Representation of Memory Space With the 78K0/KE2 products which support the memory bank, addresses can be viewed in the following two different ways. • Memory bank number + CPU address ...
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CHAPTER 4 MEMORY BANK SELECT FUNCTION ( Table 4-1. Memory Bank Address Representation Memory Bank Number CPU Address Memory bank 0 08000H-0BFFFH Memory bank 1 Memory bank 2 Memory bank 3 Memory bank 4 Memory bank 5 Notes 1. SM+ ...
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CHAPTER 4 MEMORY BANK SELECT FUNCTION ( 4.4 Selecting Memory Bank The memory bank selected by the memory bank select register (BANK) is reflected on the bank area and can be addressed. Therefore, to access a memory bank different from ...
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CHAPTER 4 MEMORY BANK SELECT FUNCTION ( • Software example (to store a value to be referenced in register A) RAMD DSEG SADDR R_BNKA R_BNKN R_BNKRN ETRC CSEG UNIT ENTRY: MOV R_BNKN,#BANKNUM DATA1 MOVW ...
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CHAPTER 4 MEMORY BANK SELECT FUNCTION ( 4.4.2 Branching instruction between memory banks Instructions cannot branch directly from one memory bank to another. To branch an instruction from one memory bank to another, branch once to the common area (0000H ...
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CHAPTER 4 MEMORY BANK SELECT FUNCTION ( • Software example 1 (to branch from all areas) RAMD DSEG SADDR R_BNKA R_BNKN RSAVEAX ETRC CSEG UNIT ENTRY: MOV R_BNKN,#BANKNUM TEST MOVW R_BNKA,#TEST BR !BNKBR : ...
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CHAPTER 4 MEMORY BANK SELECT FUNCTION ( 4.4.3 Subroutine call between memory banks Subroutines cannot be directly called between memory banks. To call a subroutine between memory banks, branch once to the common area (0000H to 7FFFH), specify the memory ...
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CHAPTER 4 MEMORY BANK SELECT FUNCTION ( • Software example RAMD DSEG SADDR R_BNKA R_BNKN R_BNKRN RSAVEAX ETRC CSEG UNIT ENTRY: MOV R_BNKN,#BANKNUM TEST MOVW R_BNKA,#TEST CALL !BNKCAL BNKC CSEG AT BNKCAL: ...
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CHAPTER 4 MEMORY BANK SELECT FUNCTION ( 4.4.4 Instruction branch to bank area by interrupt When an interrupt occurs, instructions can branch to the memory bank specified by the BANK register by using the vector table, but it is difficult ...
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CHAPTER 4 MEMORY BANK SELECT FUNCTION ( Remark Note the following points to use the memory bank select function efficiently. • Allocate a routine that is used often in the common area. • value that is planned to ...
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Port Functions There are three types of pin I/O buffer power supplies: AV power supplies and the pins is shown below. Power Supply AV REF 78K0/KE2 products are provided with the ports shown in Figure ...
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Pin Name I/O P00 I/O Port 0. 7-bit I/O port. P01 Input/output can be specified in 1-bit units. P02 Use of an on-chip pull-up resistor can be specified by a P03 software setting. P04 P05 P06 P10 I/O Port 1. ...
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Function Name I/O P120 I/O Port 12. 5-bit I/O port. P121 Input/output can be specified in 1-bit units. P122 Only for P120, use of an on-chip pull-up resistor can be P123 specified by a software setting. P124 P130 Output Port ...
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Port 0 Port 7-bit I/O port with an output latch. Port 0 can be set to the input mode or output mode in 1-bit units using port mode register 0 (PM0). When the P00 to P06 ...
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WR PU PU0 PU01 Alternate function RD WR PORT P0 Output latch (P01 PM0 PM01 Alternate function P0: Port register 0 PU0: Pull-up resistor option register 0 PM0: Port mode register 0 RD: Read signal WR××: Write signal ...
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CHAPTER 5 PORT FUNCTIONS Figure 5-4. Block Diagram of P02 WR PU PU0 PU02 RD WR PORT P0 Output latch (P02 PM0 PM02 Alternate Note function P0: Port register 0 PU0: Pull-up resistor option register 0 PM0: Port ...
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Figure 5-5. Block Diagram of P03 and P05 µ (a) PD78F0531, 78F0532, 78F0533 WR PU PU0 PU03, PU05 RD WR PORT P0 Output latch (P03, P05 PM0 PM03, PM05 µ (b) PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D WR PU ...
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PD78F0531, 78F0532, 78F0533 PORT Output latch WR PM µ (b) PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D WR PU PU0 PU04 Alternate function RD WR PORT Output latch (P04 PM0 PM04 Alternate function P0: ...
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PD78F0531, 78F0532, 78F0533 PORT Output latch WR PM µ (b) PD78F0534, 78F0535, 78F0536, 78F0537, 78F0537D WR PU PU0 PU06 Alternate function RD WR PORT P0 Output latch (P06 PM0 PM06 Alternate function ...
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Port 1 Port 8-bit I/O port with an output latch. Port 1 can be set to the input mode or output mode in 1-bit units using port mode register 1 (PM1). When the P10 to P17 ...
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Figure 5-9. Block Diagram of P11 and P14 WR PU PU1 PU11, PU14 Alternate function RD WR PORT P1 Output latch (P11, P14 PM1 PM11, PM14 P1: Port register 1 PU1: Pull-up resistor option register 1 PM1: Port ...
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CHAPTER 5 PORT FUNCTIONS Figure 5-10. Block Diagram of P12 and P15 WR PU PU1 PU12, PU15 RD WR PORT P1 Output latch (P12, P15 PM1 PM12, PM15 Alternate function P1: Port register 1 PU1: Pull-up resistor option ...
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WR PU PU1 PU13 RD WR PORT P1 Output latch (P13 PM1 PM13 Alternate function P1: Port register 1 PU1: Pull-up resistor option register 1 PM1: Port mode register 1 RD: Read signal WR××: Write signal 114 CHAPTER ...
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CHAPTER 5 PORT FUNCTIONS Figure 5-12. Block Diagram of P16 and P17 WR PU PU1 PU16, PU17 Alternate function RD WR PORT P1 Output latch (P16, P17 PM1 PM16, PM17 Alternate function P1: Port register 1 PU1: Pull-up ...
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Port 2 Port 8-bit I/O port with an output latch. Port 2 can be set to the input mode or output mode in 1-bit units using port mode register 2 (PM2). This port can also be ...
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... PD78F0534, 78F0535, 78F0536, and 78F0537) and having a product rank of “I”, “K”, or “E”, and for the product with an on-chip debug function ( OCD1A • P31/INTP2/OCD1A The above connection is not necessary when writing the flash memory by means of self programming. Note OCD1A is provided to the Remarks 1. For the product ranks, consult an NEC Electronics sales representative. ...
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Figure 5-14. Block Diagram of P30 to P32 WR PU PU3 PU30 to PU32 Alternate function RD WR PORT P3 Output latch (P30 to P32 PM3 PM30 to PM32 P3: Port register 3 PU3: Pull-up resistor option register ...
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CHAPTER 5 PORT FUNCTIONS Figure 5-15. Block Diagram of P33 WR PU PU3 PU33 Alternate function RD WR PORT P3 Output latch (P33 PM3 PM33 Alternate function P3: Port register 3 PU3: Pull-up resistor option register 3 PM3: ...
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Port 4 Port 4-bit I/O port with an output latch. Port 4 can be set to the input mode or output mode in 1-bit units using port mode register 4 (PM4). When the P40 to P43 ...
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Port 5 Port 4-bit I/O port with an output latch. Port 5 can be set to the input mode or output mode in 1-bit units using port mode register 5 (PM5). When the P50 to P53 ...
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Port 6 Port 4-bit I/O port with an output latch. Port 6 can be set to the input mode or output mode in 1-bit units using port mode register 6 (PM6). The output of the P60 ...
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CHAPTER 5 PORT FUNCTIONS Figure 5-19. Block Diagram of P62 Alternate function RD WR PORT P6 Output latch (P62 PM6 PM62 P6: Port register 6 PM6: Port mode register 6 RD: Read signal WR××: Write signal Figure 5-20. ...
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Port 7 Port 8-bit I/O port with an output latch. Port 7 can be set to the input mode or output mode in 1-bit units using port mode register 7 (PM7). When the P70 to P77 ...
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... Reset signal generation sets port 12 to input mode. Figures 5-22 and 5-23 show block diagrams of port 12. Cautions 1. When using the P121 to P124 pins to connect a resonator for the main system clock (X1, X2) or subsystem clock (XT1, XT2 input an external clock for the main system clock ...
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WR PU PU12 PU120 Alternate function RD WR PORT P12 Output latch (P120 PM12 PM120 P12: Port register 12 PU12: Pull-up resistor option register 12 PM12: Port mode register 12 RD: Read signal WR××: Write signal 126 CHAPTER ...
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Figure 5-23. Block Diagram of P121 to P124 RD WR PORT P12 Output latch (P122/P124 PM12 PM122/PM124 OSCCTL OSCSEL/ OSCSELS RD WR PORT P12 Output latch (P121/P123 PM12 PM121/PM123 OSCCTL OSCSEL/ OSCSELS P12: Port register 12 ...
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Port 13 Port 1-bit output-only port. Figure 5-24 shows a block diagram of port 13 PORT Output latch (P130) P13: Port register 13 RD: Read signal WR××: Write signal Remark When reset is effected, ...
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Port 14 Port 6-bit I/O port with an output latch. Port 14 can be set to the input mode or output mode in 1-bit units using port mode register 14 (PM14). When the P140 and P141 ...
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Registers Controlling Port Function Port functions are controlled by the following four types of registers. • Port mode registers (PM0 to PM7, PM12, PM14) • Port registers (P0 to P7, P12 to P14) • Pull-up resistor option registers (PU0, ...
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Figure 5-26. Format of Port Mode Register Symbol PM0 1 PM06 PM05 PM1 PM17 PM16 PM15 PM2 PM27 PM26 PM25 PM3 PM4 PM5 PM6 PM7 ...
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Port registers (P0 to P7, P12 to P14) These registers write the data that is output from the chip when data is output from a port. If the data is read in the input mode, the pin level is ...
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... PU0, PU1, PU3 to PU5, PU7, PU12, and PU14. On-chip pull-up resistors cannot be connected to bits set to output mode and bits used as alternate-function output pins, regardless of the settings of PU0, PU1, PU3 to PU5, PU7, PU12, and PU14 ...
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A/D port configuration register (ADPC) This register switches the P20/ANI0 to P27/ANI7 pins to digital I/O of port or analog input of A/D converter. ADPC can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation ...
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Port Function Operations Port operations differ depending on whether the input or output mode is set, as shown below. 5.4.1 Writing to I/O port (1) Output mode A value is written to the output latch by a transfer instruction, ...
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Settings of Port Mode Register and Output Latch When Using Alternate Function To use the alternate function of a port pin, set the port mode register and output latch as shown in Table 5-5. Table 5-5. Settings of Port ...
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... The X1, X2, P31, and P32 pins of the pins (OCD0A, OCD0B, OCD1A, OCD1B) when the on-chip debug function is used. For how to <R> connect an in-circuit emulator supporting on-chip debugging (QB-78K0MINI or QB-MINI2), see CHAPTER 27 ON-CHIP DEBUG FUNCTION ( (Notes 1 and 2 are listed on the next page.) ...
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... Digital I/O selection 2. When using the P121 to P124 pins to connect a resonator for the main system clock (X1, X2) or subsystem clock (XT1, XT2 input an external clock for the main system clock (EXCLK) or subsystem clock (EXCLKS), the X1 oscillation mode, XT1 oscillation mode, or external clock input mode must be set by using the clock operation mode select register (OSCCTL) (for details, see 6 ...
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Cautions on 1-Bit Manipulation Instruction for Port Register n (Pn) When a 1-bit manipulation instruction is executed on a port that provides both input and output functions, the output latch value of an input port that is not subject ...
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... XT1 clock oscillation frequency External subsystem clock frequency EXCLKS 140 CHAPTER 6 CLOCK GENERATOR = MHz by connecting a resonator to X1 and X2 MHz (TYP.). After a reset release, the CPU always starts MHz) can also be supplied from the EXCLK/X2/P122 pin. An EXCLK = 32.768 kHz by connecting a 32.768 kHz resonator across XT1 ...
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Internal low-speed oscillation clock (clock for watchdog timer) • Internal low-speed oscillator This circuit oscillates a clock of f clock always starts operating. Oscillation can be stopped by using the internal oscillation mode register (RCM) when “internal low-speed oscillator ...
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Clock operation mode Main OSC control register select register (OSCCTL) (MOC) AMPH EXCLK OSCSEL MSTOP High-speed system clock oscillator f XH X1/P121 Crystal/ceramic f X oscillation X2/EXCLK/ P122 External input f Internal high- EXCLK f clock speed oscillator (8 MHz ...
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Remarks clock oscillation frequency Internal high-speed oscillation clock frequency External main system clock frequency EXCLK High-speed system clock frequency Main system ...
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... Note Note EXCLKS OSCSELS 0 High-speed system clock P121/X1 pin pin operation mode I/O port mode I/O port X1 oscillation mode Crystal/ceramic resonator connection I/O port mode I/O port External clock input I/O port mode Operating frequency control ≤ 10 MHz XH ≤ 20 MHz XH µ ...
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Processor clock control register (PCC) This register is used to select the CPU clock, the division ratio, and operation mode for subsystem clock. PCC is set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets PCC ...
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... I/O port mode I/O port XT1 oscillation mode Crystal resonator connection I/O port mode I/O port External clock input mode I/O port XT1 oscillation mode Crystal resonator connection User’s Manual U17260EJ6V0UD CPU Subsystem Clock At 32.768 kHz Operation − − − − ...
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Internal oscillation mode register (RCM) This register sets the operation mode of internal oscillator. RCM can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets this register to 80H Figure 6-4. Format of Internal ...
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Main OSC control register (MOC) This register selects the operation mode of the high-speed system clock. This register is used to stop the X1 oscillator or to disable an external clock input from the EXCLK pin when the CPU ...
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Main clock mode register (MCM) This register selects the main system clock supplied to CPU clock and clock supplied to peripheral hardware clock. MCM can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears ...
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Oscillation stabilization time counter status register (OSTC) This is the register that indicates the count status of the X1 clock oscillation stabilization time counter. When X1 clock oscillation starts with the internal high-speed oscillation clock or subsystem clock used ...
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Oscillation stabilization time select register (OSTS) This register is used to select the X1 clock oscillation stabilization wait time when the STOP mode is released. When the X1 clock is selected as the CPU clock, the operation waits for ...
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... System Clock Oscillator 6.4.1 X1 oscillator The X1 oscillator oscillates with a crystal resonator or ceramic resonator ( MHz) connected to the X1 and X2 pins. An external clock can also be input. In this case, input the clock signal to the EXCLK pin. Figure 6-9 shows an example of the external circuit of the X1 oscillator. ...
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... Do not fetch signals from the oscillator. Note that the XT1 oscillator is designed as a low-amplitude circuit for reducing power consumption. Figure 6-11 shows examples of incorrect resonator connection. Figure 6-11. Examples of Incorrect Resonator Connection (1/2) (a) Too long wiring Remark When using the subsystem clock, replace X1 and X2 with XT1 and XT2, respectively ...
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... Figure 6-11. Examples of Incorrect Resonator Connection (2/2) (c) Wiring near high alternating current (e) Signals are fetched Remark When using the subsystem clock, replace X1 and X2 with XT1 and XT2, respectively. Also, insert resistors in series on the XT2 side. Caution 2. When X2 and XT1 are wired in parallel, the crosstalk noise of X2 may increase with XT1, resulting in malfunctioning ...
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... When subsystem clock is not used not necessary to use the subsystem clock for low power consumption operations not using the subsystem clock as an I/O port, set the XT1 and XT2 pins to I/O mode (OSCSELS = 0) and connect them as follows. Input (PM123/PM124 = 1): Independently connect to V Output (PM123/PM124 = 0): Leave open ...
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... When the X1 clock is set as the CPU clock by the default setting, the device cannot operate if the X1 clock is damaged or badly connected and therefore does not operate after reset is released. However, the start clock of the CPU is the internal high-speed oscillation clock, so the device can be started by the internal high-speed oscillation clock after a reset release ...
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Figure 6-12. Clock Generator Operation When Power Supply Voltage Is Turned On Power supply voltage ( 1. Internal reset signal <1> CPU clock Internal high-speed oscillation clock ( High-speed system clock (f ) ...
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... Caution It is not necessary to wait for the oscillation stabilization time when an external clock input from the EXCLK and EXCLKS pins is used. Remark While the microcontroller is operating, a clock that is not used as the CPU clock can be stopped via software settings ...
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... It is not necessary to wait for the oscillation stabilization time when an external clock input from the EXCLK and EXCLKS pins is used. Remark While the microcontroller is operating, a clock that is not used as the CPU clock can be stopped via software settings ...
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... The following two types of high-speed system clocks are available. • X1 clock: Crystal/ceramic resonator is connected across the X1 and X2 pins. • External main system clock: External clock is input to the EXCLK pin. When the high-speed system clock is not used, the X1/P121 and X2/EXCLK/P122 pins can be used as I/O port pins ...
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... Setting high-speed system clock oscillation (See 6.6.1 (1) Example of setting procedure when oscillating the X1 clock and (2) Example of setting procedure when using the external main system clock.) Note The setting of <1> is not necessary when high-speed system clock is already operating. CHAPTER 6 CLOCK GENERATOR ELECTRICAL SPECIFICATIONS ((A2) GRADE PRODUCTS: T Operating Frequency Control 1 MHz ≤ ...
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Setting the high-speed system clock as the main system clock (MCM register) When XSEL and MCM0 are set to 1, the high-speed system clock is supplied as the main system clock and peripheral hardware clock. XSEL MCM0 1 1 ...
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... Notes 1. After a reset release, the internal high-speed oscillator automatically starts oscillating and the internal high-speed oscillation clock is selected as the CPU clock. 2. This wait time is not necessary if high accuracy is not necessary for the CPU clock and peripheral hardware clock. (2) Example of setting procedure when using internal high-speed oscillation clock as CPU clock, and internal high-speed oscillation clock or high-speed system clock as peripheral hardware clock < ...
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... Note The setting of <1> is not necessary when the internal high-speed oscillation clock or high- speed system clock is already operating. <2> Selecting the clock supplied as the main system clock and peripheral hardware clock (MCM register) Set the main system clock and peripheral hardware clock using XSEL and MCM0. ...
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... The following two types of subsystem clocks are available. • XT1 clock: Crystal/ceramic resonator is connected across the XT1 and XT2 pins. • External subsystem clock: External clock is input to the EXCLKS pin. When the subsystem clock is not used, the XT1/P123 and XT2/EXCLKS/P124 pins can be used as I/O port pins. ...
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... Example of setting procedure when oscillating the XT1 clock and (2) Example of setting procedure when using the external subsystem clock.) Note The setting of <1> is not necessary when while the subsystem clock is operating. <2> Switching the CPU clock (PCC register) When CSS is set to 1, the subsystem clock is supplied to the CPU. ...
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Example of controlling internal low-speed oscillation clock The internal low-speed oscillation clock cannot be used as the CPU clock. Only the following peripheral hardware can operate with this clock. • Watchdog timer • 8-bit timer H1 ( ...
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CPU clock status transition diagram Figure 6-14 shows the CPU clock status transition diagram of this product. (When 1.59 V POC Mode Is Set (Option Byte: POCMODE = 0)) Internal low-speed oscillation: Operable Internal high-speed oscillation: Operating X1 oscillation/EXCLK ...
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... User’s Manual U17260EJ6V0UD SFR Register Setting OSTC OSCSEL MSTOP XSEL Register 1 0 Must be 1 checked Must not be checked 1 0 Must be 1 checked Must not be checked = −40 to +125°C)). A OSCSELS Waiting for Oscillation Stabilization 0 1 Necessary × × Unnecessary MCM0 CSS 1 1 169 ...
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... XH (B) → (C) (external main clock: 10 MHz < MHz) Note The value of this flag can be changed only once after a reset release. This setting is not necessary if it has already been set. <R> Caution Set the clock after the supply voltage has reached the operable voltage of the clock to be set (see ...
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... Remarks 1. (A) to (I) in Table 6-5 correspond to (A) to (I) in Figure 6-14. 2. MCM0: EXCLKS, OSCSELS: Bits 5 and 4 of the clock operation mode select register (OSCCTL) RSTS, RSTOP: XTSTART, CSS: ×: CHAPTER 6 CLOCK GENERATOR RSTOP 0 Confirm this flag is 1. Unnecessary if the CPU is operating with the internal high-speed oscillation clock XTSTART EXCLKS 0 0 × ...
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... MHz Note The value of this flag can be changed only once after a reset release. This setting is not necessary if it has already been set. <R> Caution Set the clock after the supply voltage has reached the operable voltage of the clock to be set (see ...
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Condition before changing CPU clock and processing after changing CPU clock Condition before changing the CPU clock and processing after changing the CPU clock are shown below. CPU Clock Before Change After Change Internal high- X1 clock Stabilization of ...
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Time required for switchover of CPU clock and main system clock By setting bits (PCC0 to PCC2) and bit 4 (CSS) of the processor clock control register (PCC), the CPU clock can be switched (between the ...
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Table 6-8. Maximum Time Required for Main System Clock Switchover Set Value Before Switchover MCM0 0 1 Caution When switching the internal high-speed oscillation clock to the high-speed system clock, bit 2 (XSEL) of MCM must be set to 1 ...
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Peripheral hardware and source clocks The following lists peripheral hardware and source clocks incorporated in the 78K0/KE2. Table 6-10. Peripheral Hardware and Source Clocks Source Clock Peripheral Hardware Clock Peripheral Hardware (f PRS 16-bit timer event counter ...
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CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 µ The PD78F0531, 78F0532, and 78F0533 incorporate 16-bit timer/event counter 00, and the 78F0535, 78F0536, 78F0537, and 78F0537D incorporate 16-bit timer/event counters 00 and 01. 7.1 Functions of 16-Bit Timer/Event Counters 00 ...
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CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 7.2 Configuration of 16-Bit Timer/Event Counters 00 and 01 16-bit timer/event counters 00 and 01 include the following hardware. Table 7-1. Configuration of 16-Bit Timer/Event Counters 00 and 01 Item Time/counter Register ...
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Figure 7-2. Block Diagram of 16-Bit Timer/Event Counter 01 (Available only in the Capture/compare control register 01 (CRC01) To CR011 Noise elimi- TI011/TO01/P06 nator f PRS PRS PRS Noise f 2 elimi- PRS ...
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CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-3. Format of 16-Bit Timer Counter 0n (TM0n) Address: FF10H, FF11H (TM00), FFB0H, FFB1H (TM01) FF11H (TM00), FFB1H (TM01 TM0n ( The count value of ...
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CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-4. Format of 16-Bit Timer Capture/Compare Register 00n (CR00n) Address: FF12H, FF13H (CR000), FFB2H, FFB3H (CR001) FF13H (CR000), FFB3H (CR001 CR00n ( (i) When ...
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CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 (iii) Setting range when CR00n or CR01n is used as a compare register When CR00n or CR01n is used as a compare register, set it as shown below. Operation Operation as interval ...
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CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Table 7-2. Capture Operation of CR00n and CR01n External Input Signal TI00n Pin Input Capture Operation Capture operation of CRC0n1 = 1 CR00n TI00n pin input (reverse phase) Interrupt signal Note Capture ...
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CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 7.3 Registers Controlling 16-Bit Timer/Event Counters 00 and 01 Registers used to control 16-bit timer/event counters 00 and 01 are shown below. • 16-bit timer mode control register 0n (TMC0n) • Capture/compare ...
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CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-6. Format of 16-Bit Timer Mode Control Register 00 (TMC00) Address: FFBAH After reset: 00H R/W Symbol 7 6 TMC00 0 0 TMC003 TMC002 ...
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CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-7. Format of 16-Bit Timer Mode Control Register 01 (TMC01) Address: FFB6H After reset: 00H Symbol 7 6 TMC01 0 0 TMC013 TMC012 ...
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CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 (2) Capture/compare control register 0n (CRC0n) CRC0n is the register that controls the operation of CR00n and CR01n. Changing the value of CRC0n is prohibited during operation (when TMC0n3 and TMC0n2 = ...
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CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-9. Example of CR01n Capture Operation (When Rising Edge Is Specified) Count clock TM0n TI00n Rising edge detection CR01n INTTM01n µ Remark PD78F0531, 78F0532, 78F0533 µ ...
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TOC0n is an 8-bit register that controls the TO0n output. TOC0n can be rewritten while only OSPT0n is operating (when TMC0n3 and TMC0n2 = other than 00). Rewriting the other bits ...
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CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-11. Format of 16-Bit Timer Output Control Register 00 (TOC00) Address: FFBDH After reset: 00H Symbol 7 TOC00 0 OSPT00 OSPT00 0 1 One-shot pulse output The value of this bit ...
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Figure 7-12. Format of 16-Bit Timer Output Control Register 01 (TOC01) Address: FFB9H After reset: 00H Symbol 7 TOC01 0 OSPT01 0 1 The value of this bit is always 0 when it is read. Do not set this bit ...
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CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 (4) Prescaler mode register 0n (PRM0n) PRM0n is the register that sets the TM0n count clock and TI00n and TI01n pin input valid edges. Rewriting PRM0n is prohibited during operation (when TMC0n3 ...
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Address: FFBBH After reset: 00H Symbol 7 PRM00 ES101 ES101 ES001 PRM001 <R> Notes 1. If the peripheral hardware clock (f f operating frequency varies depending on the ...
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CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-14. Format of Prescaler Mode Register 01 (PRM01) Address: FFB7H After reset: 00H Symbol 7 PRM01 ES111 ES111 ES011 PRM011 PRM010 0 0 ...
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CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 (5) Port mode register 0 (PM0) This register sets port 0 input/output in 1-bit units. When using the P01/TO00/TI010 and P06/TO01/TI011 pins for timer output, set PM01 and PM06 and the output ...
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CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 7.4 Operation of 16-Bit Timer/Event Counters 00 and 01 7.4.1 Interval timer operation If bits 3 and 2 (TMC0n3 and TMC0n2) of the 16-bit timer mode control register (TMC0n) are set to ...
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CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-18. Example of Register Settings for Interval Timer Operation (a) 16-bit timer mode control register 0n (TMC0n (b) Capture/compare control register 0n (CRC0n ...
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CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-19. Example of Software Processing for Interval Timer Function TM0n register 0000H Operable bits 00 (TMC0n3, TMC0n2) CR00n register INTTM00n signal <1> Count operation start flow START Register initial setting PRM0n ...
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Square-wave output operation When 16-bit timer/event counter 0n operates as an interval timer (see 7.4.1), a square wave can be output from the TO0n pin by setting the 16-bit timer output control register 0n (TOC0n) to 03H. When TMC0n3 ...
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CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01 Figure 7-22. Example of Register Settings for Square-Wave Output Operation (a) 16-bit timer mode control register 0n (TMC0n (b) Capture/compare control register 0n (CRC0n <R> (c) ...