UPD78F0537DGA(T)-9EV-A NEC, UPD78F0537DGA(T)-9EV-A Datasheet - Page 185
UPD78F0537DGA(T)-9EV-A
Manufacturer Part Number
UPD78F0537DGA(T)-9EV-A
Description
8BIT MCU, 128K FLASH, 7KB RAM, SMD
Manufacturer
NEC
Datasheet
1.UPD78F0535GBT-UEU-A.pdf
(773 pages)
Specifications of UPD78F0537DGA(T)-9EV-A
Controller Family/series
UPD78
No. Of I/o's
55
Ram Memory Size
7KB
Cpu Speed
20MHz
No. Of Timers
8
No. Of Pwm
RoHS Compliant
Core Size
8bit
Program Memory Size
128KB
Oscillator Type
External, Internal
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Address: FFBAH
Note The TI000 pin valid edge is set by bits 5 and 4 (ES001, ES000) of prescaler mode register 00 (PRM00).
Symbol
TMC00
OVF00 is set to 1 when the value of TM00 changes from FFFFH to 0000H in all the operation modes (free-running
timer mode, clear & start mode entered by TI000 pin valid edge input, and clear & start mode entered upon a match
between TM00 and CR000).
It can also be set to 1 by writing 1 to OVF00.
TMC001
Clear (0)
TMC003
OVF00
Set (1)
0
1
0
0
1
1
7
0
After reset: 00H
Figure 7-6. Format of 16-Bit Timer Mode Control Register 00 (TMC00)
• Match between TM00 and CR000 or match between TM00 and CR010
• Match between TM00 and CR000 or match between TM00 and CR010
• Trigger input of TI000 pin valid edge
Clears OVF00 to 0 or TMC003 and TMC002 = 00
Overflow occurs.
TMC002
CHAPTER 7 16-BIT TIMER/EVENT COUNTERS 00 AND 01
0
1
0
1
6
0
R/W
Disables 16-bit timer/event counter 00 operation. Stops supplying operating clock.
Clears 16-bit timer counter 00 (TM00).
Free-running timer mode
Clear & start mode entered by TI000 pin valid edge input
Clear & start mode entered upon a match between TM00 and CR000
5
0
User’s Manual U17260EJ6V0UD
Condition to reverse timer output (TO00)
Operation enable of 16-bit timer/event counter 00
4
0
TM00 overflow flag
TMC003
3
TMC002
2
Note
TMC001
1
OVF00
<0>
185
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