UPD78F0537DGA(T)-9EV-A NEC, UPD78F0537DGA(T)-9EV-A Datasheet - Page 390

• Manufacturer Part Number: UPD78F0537DGA(T)-9EV-A
• Description: 8BIT MCU, 128K FLASH, 7KB RAM, SMD
• Manufacturer: NEC

Specifications of UPD78F0537DGA(T)-9EV-A

• Controller Family/series: UPD78
• No. Of I/o's: 55
• Ram Memory Size: 7KB
• Cpu Speed: 20MHz
• No. Of Timers: 8
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 128KB
• Oscillator Type: External, Internal

390
Therefore, the maximum receivable baud rate at the transmission destination is as follows.
Similarly, the maximum permissible data frame length can be calculated as follows.
Therefore, the minimum receivable baud rate at the transmission destination is as follows.
The permissible baud rate error between UART6 and the transmission destination can be calculated from the
above minimum and maximum baud rate expressions, as follows.
Remarks 1. The permissible error of reception depends on the number of bits in one frame, input clock
10
11
4
8
20
50
100
255
Minimum permissible data frame length: FLmin = 11 × FL −
× FLmax = 11 × FL −
Division Ratio (k)
FLmax =
BRmax = (FLmin/11)
BRmin = (FLmax/11)
2. k: Set value of BRGC6
frequency, and division ratio (k). The higher the input clock frequency and the higher the division
ratio (k), the higher the permissible error.
21k – 2
20k
Table 15-6. Maximum/Minimum Permissible Baud Rate Error
FL × 11
k + 2
2 × k
Maximum Permissible Baud Rate Error
−
−
× FL =
1
1
CHAPTER 15 SERIAL INTERFACE UART6
=
=
21k + 2
21k − 2
22k
20k
21k − 2
+2.33%
+3.53%
+4.26%
+4.56%
+4.66%
+4.72%
2 × k
User’s Manual U17260EJ6V0UD
Brate
Brate
FL
k − 2
2k
× FL =
Minimum Permissible Baud Rate Error
21k + 2
2k
−2.44%
−3.61%
−4.31%
−4.58%
−4.67%
−4.73%
FL