UPD78F0537DGA(T)-9EV-A NEC, UPD78F0537DGA(T)-9EV-A Datasheet - Page 168

• Manufacturer Part Number: UPD78F0537DGA(T)-9EV-A
• Description: 8BIT MCU, 128K FLASH, 7KB RAM, SMD
• Manufacturer: NEC

Specifications of UPD78F0537DGA(T)-9EV-A

• Controller Family/series: UPD78
• No. Of I/o's: 55
• Ram Memory Size: 7KB
• Cpu Speed: 20MHz
• No. Of Timers: 8
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 128KB
• Oscillator Type: External, Internal

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6.6.6 CPU clock status transition diagram
168
Internal low-speed oscillation: Operable
Internal high-speed oscillation:
Selectable by CPU
X1 oscillation/EXCLK input:
Selectable by CPU
XT1 oscillation/EXCLKS input: Operating
Figure 6-14 shows the CPU clock status transition diagram of this product.
Note 1.8 V (Standard and (A) grade products), 2.7 V ((A2) grade products)
Remark In the 2.7 V/1.59 V POC mode (option byte: POCMODE = 1), the CPU clock status changes to (A) in the
Internal low-speed oscillation: Operable
Internal high-speed oscillation: Operable
X1 oscillation/EXCLK input: Operable
XT1 oscillation/EXCLKS input:
Operating
above figure when the supply voltage exceeds 2.7 V (TYP.), and to (B) after reset processing (11 to 45
µ
s).
(D)
(When 1.59 V POC Mode Is Set (Option Byte: POCMODE = 0))
(G)
with XT1 oscillation or
oscillation/EXCLKS
Internal low-speed oscillation: Operable
Internal high-speed oscillation: Operating
X1 oscillation/EXCLK input:
Selectable by CPU
XT1 oscillation/EXCLKS input:
Selectable by CPU
CPU: Operating
input → HALT
EXCLKS input
CPU: XT1
Figure 6-14. CPU Clock Status Transition Diagram
Internal low-speed oscillation: Operable
Internal high-speed oscillation:
Selectable by CPU
X1 oscillation/EXCLK input: Operating
XT1 oscillation/EXCLKS input:
Selectable by CPU
CHAPTER 6 CLOCK GENERATOR
User’s Manual U17260EJ6V0UD
(A)
(B)
(C)
with X1 oscillation or
Reset release
with internal high-
speed oscillation
CPU: Operating
CPU: Operating
Power ON
EXCLK input
(F)
oscillation/EXCLK
input → HALT
CPU: X1
Internal low-speed oscillation:
Operable
Internal high-speed oscillation:
Operable
X1 oscillation/EXCLK input: Operating
XT1 oscillation/EXCLKS input: Operable
Internal low-speed oscillation: Woken up
Internal high-speed oscillation: Woken up
X1 oscillation/EXCLK input: Stops (I/O port mode)
XT1 oscillation/EXCLKS input: Stops (I/O port mode)
Internal low-speed oscillation: Operating
Internal high-speed oscillation: Operating
X1 oscillation/EXCLK input: Stops (I/O port mode)
XT1 oscillation/EXCLKS input: Stops (I/O port mode)
(H)
(E)
(I)
CPU: Internal high-
oscillation/EXCLK
CPU: Internal high-
speed oscillation
speed oscillation
input → STOP
V
V
V
→ STOP
CPU: X1
DD
DD
DD
→ HALT
< 1.59 V (TYP.)
≥ 1.59 V (TYP.)
≥ 1.8 V (MIN.)
Internal low-speed oscillation:
Operable
Internal high-speed oscillation:
Stops
X1 oscillation/EXCLK input: Stops
XT1 oscillation: Operable
Note
Internal low-speed oscillation:
Operable
Internal high-speed oscillation:
Stops
X1 oscillation/EXCLK input: Stops
XT1 oscillation/EXCLKS input:
Operable
Internal low-speed oscillation:
Operable
Internal high-speed oscillation:
Operating
X1 oscillation/EXCLK input: Operable
XT1 oscillation/EXCLKS input:
Operable