UPD78F0537DGA(T)-9EV-A NEC, UPD78F0537DGA(T)-9EV-A Datasheet - Page 754

• Manufacturer Part Number: UPD78F0537DGA(T)-9EV-A
• Description: 8BIT MCU, 128K FLASH, 7KB RAM, SMD
• Manufacturer: NEC

Specifications of UPD78F0537DGA(T)-9EV-A

• Controller Family/series: UPD78
• No. Of I/o's: 55
• Ram Memory Size: 7KB
• Cpu Speed: 20MHz
• No. Of Timers: 8
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 128KB
• Oscillator Type: External, Internal

754
CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11
pp. 398, 399
p. 400
CHAPTER 17 SERIAL INTERFACE IIC0
p. 415
p. 432
CHAPTER 18 MULTIPLIER/DIVIDER (
p. 487
CHAPTER 19 INTERRUPT FUNCTIONS
p. 497
p. 502
CHAPTER 23 POWER-ON-CLEAR CIRCUIT
p. 542
p. 543
CHAPTER 24 LOW-VOLTAGE DETECTOR
p. 547
p. 548
p. 549
p. 549
pp. 557, 558
p. 560
pp. 562, 563
CHAPTER 25 OPTION BYTE
p. 564
CHAPTER 26 FLASH MEMORY
pp. 586, 587
pp. 590 to 594 Modification of Table 26-13 Processing Time for Self Programming Library and Table 26-14
p. 595
p. 595
p. 596
Remark “Classification” in the above table classifies revisions as follows.
Page
(a): Error correction, (b): Addition/change of specifications, (c): Addition/change of description or note,
(d): Addition/change of package, part number, or management division, (e): Addition/change of related
documents
Addition of Notes 1 and 2 to Figure 16-5 Format of Serial Clock Selection Register 10
(CSIC10)
Addition of Notes 1 and 2 to Figure 16-6 Format of Serial Clock Selection Register 11
(CSIC11)
Addition of Caution to 17.1 Functions of Serial Interface IIC0
Addition of Notes 1 and 2 to Table 17-2 Selection Clock Setting
Addition of Caution before 18.1 Functions of Multiplier/Divider
Modification of Note 4 to Table 19-1 Interrupt Source List (1/2)
Modification of Note 1 in Table 19-2 Flags Corresponding to Interrupt Request Sources
Modification of Notes 1 and 2 in and addition of Note 3 to Figure 23-2 Timing of Generation of
Internal Reset Signal by Power-on-Clear Circuit and Low-Voltage Detector (1/2)
Modification of Notes 1 in Figure 23-2 Timing of Generation of Internal Reset Signal by
Power-on-Clear Circuit and Low-Voltage Detector (2/2)
Modification of explanation in 24.3 (1) Low-voltage detection register (LVIM)
Addition of Notes 1 and 4 and Cautions 3 and 4 to Figure 24-2 Format of Low-Voltage
Detection Register (LVIM)
Modification of explanation in 24.3 (2) Low-voltage detection level selection register (LVIS)
Addition of Notes 1 and 2 and Caution 4 to Figure 24-3 Format of Low-Voltage Detection
Level Selection Register (LVIS)
Addition of Note 3 to Figure 24-7 Timing of Low-Voltage Detector Interrupt Signal Generation
(Detects Level of Supply Voltage (V
Addition of Note 3 to Figure 24-8 Timing of Low-Voltage Detector Interrupt Signal Generation
(Detects Level of Input Voltage from External Input Pin (EXLVI))
Modification of explanation in Figure 24-9 Example of Software Processing After Reset
Release
Modification of explanation in 25.1 (2) 0081H/1081H
Partial modification of and addition of Caution to Table 26-12 Processing Time for Each
Command When PG-FP4 Is Used (Reference)
Interrupt Response Time for Self Programming Library
Addition of Caution to 26.10.1 Boot swap function
Modification of and addition of Remark to Figure 26-17 Boot Swap Function
Modification of Figure 26-18 Example of Executing Boot Swapping
µ
PD78F0534, 78F0535, 78F0536, 78F0537, AND 78F0537D ONLY)
APPENDIX E REVISION HISTORY
User’s Manual U17260EJ6V0UD
DD
))
Description
Classification
(b, c)
(b, c)
(a, c)
(b)
(d)
(d)
(d)
(c)
(c)
(c)
(c)
(c)
(c)
(c)
(c)
(c)
(c)
(c)
(c)
(c)
(c)
(c)
(3/5)