UPD78F0537DGA(T)-9EV-A NEC, UPD78F0537DGA(T)-9EV-A Datasheet - Page 480
UPD78F0537DGA(T)-9EV-A
Manufacturer Part Number
UPD78F0537DGA(T)-9EV-A
Description
8BIT MCU, 128K FLASH, 7KB RAM, SMD
Manufacturer
NEC
Datasheet
1.UPD78F0535GBT-UEU-A.pdf
(773 pages)
Specifications of UPD78F0537DGA(T)-9EV-A
Controller Family/series
UPD78
No. Of I/o's
55
Ram Memory Size
7KB
Cpu Speed
20MHz
No. Of Timers
8
No. Of Pwm
RoHS Compliant
Core Size
8bit
Program Memory Size
128KB
Oscillator Type
External, Internal
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17.6 Timing Charts
slave devices as its communication partner.
which specifies the data transfer direction, and then starts serial communication with the slave device.
transmit data is transferred to the SO0 latch and is output (MSB first) via the SDA0 pin.
480
When using the I
After outputting the slave address, the master device transmits the TRC0 bit (bit 3 of IIC status register 0 (IICS0)),
Figures 17-27 and 17-28 show timing charts of the data communication.
IIC shift register 0 (IIC0)’s shift operation is synchronized with the falling edge of the serial clock (SCL0). The
Data input via the SDA0 pin is captured into IIC0 at the rising edge of SCL0.
2
C bus mode, the master device outputs an address via the serial bus to select one of several
CHAPTER 17 SERIAL INTERFACE IIC0
User’s Manual U17260EJ6V0UD
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