UPD78F0537DGA(T)-9EV-A NEC, UPD78F0537DGA(T)-9EV-A Datasheet - Page 729

• Manufacturer Part Number: UPD78F0537DGA(T)-9EV-A
• Description: 8BIT MCU, 128K FLASH, 7KB RAM, SMD
• Manufacturer: NEC

Specifications of UPD78F0537DGA(T)-9EV-A

• Controller Family/series: UPD78
• No. Of I/o's: 55
• Ram Memory Size: 7KB
• Cpu Speed: 20MHz
• No. Of Timers: 8
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 128KB
• Oscillator Type: External, Internal

Port
function
Clock
generator
Function
1-bit
manipulation
instruction for
port register n
(Pn)
OSCCTL: Clock
operation mode
select register
PCC: Processor
clock control
register
RCM: Internal
oscillation mode
register
MOC: Main OSC
control register
MCM: Main
clock mode
register
Details of
Function
When a 1-bit manipulation instruction is executed on a port that provides both
input and output functions, the output latch value of an input port that is not
subject to manipulation may be written in addition to the targeted bit.
Therefore, it is recommended to rewrite the output latch when switching a port
from input mode to output mode.
Be sure to set AMPH to 1 if the high-speed system clock oscillation frequency
exceeds 10 MHz.
Set AMPH before setting the peripheral functions after a reset release. The value of
AMPH can be changed only once after a reset release. When the high-speed system
clock (X1 oscillation) is selected as the CPU clock, supply of the CPU clock is stopped
for 4.06 to 16.12
(external clock input) is selected as the CPU clock, supply of the CPU clock is stopped
for the duration of 160 external clocks after AMPH is set to 1.
If the STOP instruction is executed when AMPH = 1, supply of the CPU clock is
stopped for 4.06 to 16.12
high-speed oscillation clock is selected as the CPU clock, or for the duration of
160 external clocks when the high-speed system clock (external clock input) is
selected as the CPU clock. When the high-speed system clock (X1 oscillation) is
selected as the CPU clock, the oscillation stabilization time is counted after the
STOP mode is released.
To change the value of EXCLK and OSCSEL, be sure to confirm that bit 7
(MSTOP) of the main OSC control register (MOC) is 1 (the X1 oscillator stops or
the external clock from the EXCLK pin is disabled).
Be sure to clear bits 3 and 7 to “0”.
Confirm that bit 5 (CLS) of the processor clock control register (PCC) is 0 (CPU is
operating with main system clock) when changing the current values of XTSTART,
EXCLKS, and OSCSELS.
When setting RSTOP to 1, be sure to confirm that the CPU operates with a clock
other than the internal high-speed oscillation clock. Specifically, set under either
of the following conditions.
• When MCS = 1 (when CPU operates with the high-speed system clock)
• When CLS = 1 (when CPU operates with the subsystem clock)
In addition, stop peripheral hardware that is operating on the internal high-speed
oscillation clock before setting RSTOP to 1.
When setting MSTOP to 1, be sure to confirm that the CPU operates with a clock
other than the high-speed system clock. Specifically, set under either of the
following conditions.
• When MCS = 0 (when CPU operates with the internal high-speed oscillation
• When CLS = 1 (when CPU operates with the subsystem clock)
In addition, stop peripheral hardware that is operating on the high-speed system
clock before setting MSTOP to 1.
Do not clear MSTOP to 0 while bit 6 (OSCSEL) of the clock operation mode select
register (OSCCTL) is 0 (I/O port mode).
The peripheral hardware cannot operate when the peripheral hardware clock is
stopped. To resume the operation of the peripheral hardware after the peripheral
hardware clock has been stopped, initialize the peripheral hardware.
XSEL can be changed only once after a reset release.
A clock other than f
of the setting of XSEL and MCM0.
• Watchdog timer (operates with internal low-speed oscillation clock)
• When “f
• Peripheral hardware selects the external clock as the clock source
clock)
(operates with internal low-speed oscillation clock)
(Except when the external count clock of TM0n (n = 0, 1) is selected (TI00n pin
valid edge))
APPENDIX D LIST OF CAUTIONS
RL
”, “f
User’s Manual U17260EJ6V0UD
RL
µ
/2
s after AMPH is set to 1. When the high-speed system clock
PRS
7
”, or “f
is supplied to the following peripheral functions regardless
µ
RL
s after the STOP mode is released when the internal
/2
9
” is selected as the count clock for 8-bit timer H1
Cautions
p. 139
p. 144
p. 144
p. 144
p. 144
p. 145
p. 146
p. 147
p. 148
p. 148
p. 148
p. 149
p. 149
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