UPD78F0537DGA(T)-9EV-A NEC, UPD78F0537DGA(T)-9EV-A Datasheet - Page 745

• Manufacturer Part Number: UPD78F0537DGA(T)-9EV-A
• Description: 8BIT MCU, 128K FLASH, 7KB RAM, SMD
• Manufacturer: NEC

Specifications of UPD78F0537DGA(T)-9EV-A

• Controller Family/series: UPD78
• No. Of I/o's: 55
• Ram Memory Size: 7KB
• Cpu Speed: 20MHz
• No. Of Timers: 8
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 128KB
• Oscillator Type: External, Internal

Multiplier/
divider
( µ PD78F
0534,
78F0535,
78F0356,
78F0357,
78F0537D
only)
Interrupt
function
Function
SDR0: Remainder
data register 0
MDA0H, MDA0L:
Multiplication/
division data register
A0
MDB0:
Multiplication/
division data register
B0
DMUC0:
Multiplier/divider
control register 0
1F0L, 1F0L, 1F1L,
1F1H: Interrupt
request flag
registers
Details of Function
Do not use serial interface IIC0 and the multiplier/divider simultaneously, because
various flags corresponding to interrupt request sources are shared among serial
interface IIC0 and the multiplier/divider.
The value read from SDR0 during operation processing (while bit 7 (DMUE) of
multiplier/divider control register 0 (DMUC0) is 1) is not guaranteed.
SDR0 is reset when the operation is started (when DMUE is set to 1).
MDA0H is cleared to 0 when an operation is started in the multiplication mode
(when multiplier/divider control register 0 (DMUC0) is set to 81H).
Do not change the value of MDA0 during operation processing (while bit 7
(DMUE) of multiplier/divider control register 0 (DMUC0) is 1). Even in this case,
the operation is executed, but the result is undefined.
The value read from MDA0 during operation processing (while DMUE is 1) is not
guaranteed.
Do not change the value of MDB0 during operation processing (while bit 7
(DMUE) of multiplier/divider control register 0 (DMUC0) is 1). Even in this case,
the operation is executed, but the result is undefined.
Do not clear MDB0 to 0000H in the division mode. If set, undefined operation
results are stored in MDA0 and SDR0.
If DMUE is cleared to 0 during operation processing (when DMUE is 1), the
operation result is not guaranteed. If the operation is completed while the
clearing instruction is being executed, the operation result is guaranteed,
provided that the interrupt flag is set.
Do not change the value of DMUSEL0 during operation processing (while DMUE
is 1). If it is changed, undefined operation results are stored in
multiplication/division data register A0 (MDA0) and remainder data register 0
(SDR0).
If DMUE is cleared to 0 during operation processing (while DMUE is 1), the
operation processing is stopped. To execute the operation again, set
multiplication/division data register A0 (MDA0), multiplication/division data
register B0 (MDB0), and multiplier/divider control register 0 (DMUC0), and start
the operation (by setting DMUE to 1).
Be sure to clear bits 1 to 7 of 1F1H to 0 for
78F0533. Be sure to clear bits 4 to 7 of 1F1H to 0 for
78F0536, 78F0537, and 78F0537D.
When operating a timer, serial interface, or A/D converter after standby release,
operate it once after clearing the interrupt request flag. An interrupt request flag
may be set by noise.
When manipulating a flag of the interrupt request flag register, use a 1-bit
memory manipulation instruction (CLR1). When describing in C language, use a
bit manipulation instruction such as “IF0L.0 = 0;” or “_asm(“clr1 IF0L, 0”);”
because the compiled assembler must be a 1-bit memory manipulation instruction
(CLR1).
If a program is described in C language using an 8-bit memory manipulation
instruction such as “IF0L &= 0xfe;” and compiled, it becomes the assembler of
three instructions.
In this case, even if the request flag of another bit of the same interrupt request
flag register (IF0L) is set to 1 at the timing between “mov a, IF0L” and “mov IF0L,
a”, the flag is cleared to 0 at “mov IF0L, a”. Therefore, care must be exercised
when using an 8-bit memory manipulation instruction in C language.
mov a, IF0L
and a, #0FEH
mov IF0L, a
APPENDIX D LIST OF CAUTIONS
User’s Manual U17260EJ6V0UD
Cautions
µ
PD78F0531, 78F0532, and
µ
PD78F0534, 78F0535,
p. 487
p. 489
p. 489
p. 489
p. 489
p. 489
p. 490
p. 490
p. 491
p. 491
p. 491
p. 503
p. 503
p. 503
(19/25)
Page
745