UPD78F0537DGA(T)-9EV-A NEC, UPD78F0537DGA(T)-9EV-A Datasheet - Page 527

• Manufacturer Part Number: UPD78F0537DGA(T)-9EV-A
• Description: 8BIT MCU, 128K FLASH, 7KB RAM, SMD
• Manufacturer: NEC

Specifications of UPD78F0537DGA(T)-9EV-A

• Controller Family/series: UPD78
• No. Of I/o's: 55
• Ram Memory Size: 7KB
• Cpu Speed: 20MHz
• No. Of Timers: 8
• No. Of Pwm: RoHS Compliant
• Core Size: 8bit
• Program Memory Size: 128KB
• Oscillator Type: External, Internal

Cautions 1. To use the peripheral hardware that stops operation in the STOP mode, and the peripheral
(2) STOP mode release
Notes 1. When AMPH = 1
High-speed system
clock (X1 oscillation)
is selected as CPU
clock when STOP
instruction is executed
High-speed system
clock (external clock
input) is selected as
CPU clock when STOP
instruction is executed
Internal high-speed
oscillation clock is
selected as CPU clock
when STOP instruction
is executed
High-speed system
clock (X1 oscillation)
High-speed system
clock (external clock
input)
Internal high-speed
oscillation clock
2. Even if “internal low-speed oscillator can be stopped by software” is selected by the option
3. To shorten oscillation stabilization time after the STOP mode is released when the CPU operates
4. If the STOP instruction is executed when AMPH = 1, supply of the CPU clock is stopped for 4.06
2. The wait time is as follows:
Figure 21-5. Operation Timing When STOP Mode Is Released (When Unmasked Interrupt Request
hardware for which the clock that stops oscillating in the STOP mode after the STOP mode is
released, restart the peripheral hardware.
byte, the internal low-speed oscillation clock continues in the STOP mode in the status before
the STOP mode is set. To stop the internal low-speed oscillator’s oscillation in the STOP mode,
stop it by software and then execute the STOP instruction.
with the high-speed system clock (X1 oscillation), temporarily switch the CPU clock to the
internal high-speed oscillation clock before the next execution of the STOP instruction. Before
changing the CPU clock from the internal high-speed oscillation clock to the high-speed system
clock (X1 oscillation) after the STOP mode is released, check the oscillation stabilization time
with the oscillation stabilization time counter status register (OSTC).
to 16.12
selected as the CPU clock, or for the duration of 160 external clocks when the high-speed
system clock (external clock input) is selected as the CPU clock.
• When vectored interrupt servicing is carried out:
• When vectored interrupt servicing is not carried out:
STOP mode
µ
s after the STOP mode is released when the internal high-speed oscillation clock is
STOP mode release
Is Generated)
Wait for oscillation accuracy
(oscillation stabilization time set by OSTS)
stabilization (86 to 361 s)
CHAPTER 21 STANDBY FUNCTION
Supply of the CPU clock is stopped (4.06 to 16.12 s)
Supply of the CPU clock is stopped (160 external clocks)
HALT status
User’s Manual U17260EJ6V0UD
Internal high-speed
Wait
oscillation clock
Wait
Note2
µ
Note2
Clock switched by software
Clock switched by software
2 or 3 clocks
8 or 9 clocks
High-speed system clock
High-speed system clock
High-speed system clock
µ
Note1
Note1
527